Intel Broadwell-K & Skylake (non-K) desktop CPUs to launch in Q2-2015

[Homeles]

I'm dreaming of a 3-core i3 since ages, let's upgrade those ugly core count and match the nomenclature!

Intel's shown that they're fine with odd core configurations, with the native 15 core IVB-EX die. I don't think they'd ever do that, though

 

[SAAA]

That's not what the Skylake leak shows: http://vr-zone.com/articles/new-details-intels-skylake-revealed/76848.html

Under LGA S it says: 4+2, 2+2, 4+4e.

Hmm at this point my only hope is for 3/4-way SMT or more... 2 core 6/8 threads yeah! The 2 core 2 threads really need to be relegated as celeron or lower end parts in 2015...

 

[Anth Seebel]

I bet Intel have a cpu that is >100% IPC than Haswell arch. However, they will continue to release cpus every 12mths with ~5% IPC , all to milk the market for what it's worth. My OC'd haswell will be fine till 2016 (at the very least), I will not play the intel milking game.

 

[ShintaiDK]

I bet Intel have a cpu that is >100% IPC than Haswell arch. However, they will continue to release cpus every 12mths with ~5% IPC , all to milk the market for what it's worth. My OC'd haswell will be fine till 2016 (at the very least), I will not play the intel milking game.

If you believe that I got some public bridges to sell you.

 

[witeken]

I bet Intel have a cpu that is >100% IPC than Haswell arch. However, they will continue to release cpus every 12mths with ~5% IPC , all to milk the market for what it's worth. My OC'd haswell will be fine till 2016 (at the very least), I will not play the intel milking game.

Indeed, and it's called Skylake. It will have 2x as much FLOPS.

 

[Haserath]

I'd be thrilled if dual cores were finally starting to be phased out. I just don't see that happening yet, though.

I'd like to see them bring Core quads down to $130 and use Atom for $100 and below.

 

[NTMBK]

Indeed, and it's called Skylake. It will have 2x as much FLOPS.

FLOPs != IPC! Skylake will probably have almost the same IPC as Haswell, but some of those instructions (AVX-512) will process twice as much data as the Haswell equivalents.

 

[mikk]

FLOPs != IPC! Skylake will probably have almost the same IPC as Haswell, but some of those instructions (AVX-512) will process twice as much data as the Haswell equivalents.

Do you have more infos about the uarch changes in Skylake?

 

[frozentundra123456]

Unfortunately, I am becoming much less optimistic of a good performance increase from Skylake if the rumors are correct that Broadwell K and non-overclockable Skylake are coming out in the same time frame. If Skylake is really a good performance improvement, I dont see the point of bringing out the K models only for the previous generation. I am starting to think that skylake will be another marginal desktop improvement with the focus on igp and low power.

 

[witeken]

Unfortunately, I am becoming much less optimistic of a good performance increase from Skylake if the rumors are correct that Broadwell K and non-overclockable Skylake are coming out in the same time frame. If Skylake is really a good performance improvement, I dont see the point of bringing out the K models only for the previous generation. I am starting to think that skylake will be another marginal desktop improvement with the focus on igp and low power.

I don't see any correlation between the availability of K CPUs and the IPC improvements of the succeeding generation. Instead, I think Skylake might be a quite nice upgrade. We already know AVX3.2 and some othe things, and I think 14nm (Broadwell) will push Core into the mobile markets, and Intel will also have Broxton, so I don't think there's an immediate need for yet another very mobile focused update. Of course Intel keeps focusing on efficiency, but I don't think Skylake will be Haswell II, so that's why Broadwell is a lower priority for desktop.

 

[AtenRa]

Unfortunately, I am becoming much less optimistic of a good performance increase from Skylake if the rumors are correct that Broadwell K and non-overclockable Skylake are coming out in the same time frame. If Skylake is really a good performance improvement, I dont see the point of bringing out the K models only for the previous generation. I am starting to think that skylake will be another marginal desktop improvement with the focus on igp and low power.

The game has changed moving to iGPUs, you will see 5-10% IPC and 50%+ for the iGPU performance from now on in the mainstream segment. iGPU die area will get bigger than CPU cores if not with Broadwell definitely with Skylake.
I will give another two family releases (2016) for the mainstream Intel SKUs(BW and Skylake) until enthusiasts will start to move to High-End 6-8 Core SKUs and socket 2011 and beyond.
Unless Intel deliberately price 6-8 cores higher than $500, the mainstream segment will not serve enthusiasts and High-End gamers in a few years.

 

[NTMBK]

Do you have more infos about the uarch changes in Skylake?

No, which is why I said "probably" But the only big thing we have heard about is AVX-512. I wouldn't expect Skylake to be a massive deviation from the Pentium III derived line of designs.

 

[NTMBK]

I don't see any correlation between the availability of K CPUs and the IPC improvements of the succeeding generation. Instead, I think Skylake might be a quite nice upgrade. We already know AVX3.2 and some othe things...

AVX3.2 does not change IPC! IPC = instructions per clock. Throughput in terms of number of instructions. AVX3.2 increases the work done per instruction. This is the whole point of SIMD.

 

[witeken]

AVX3.2 does not change IPC! IPC = instructions per clock. Throughput in terms of number of instructions. AVX3.2 increases the work done per instruction. This is the whole point of SIMD.

Thank you for clarifying, but I didn't give AVX3.2 as an example of IPC improvements, just a general example of improvements with Skylake (AVX3.2 is a huge ISA update), since we don't know anything about the architecture.

 

[AtenRa]

AVX3.2 does not change IPC! IPC = instructions per clock. Throughput in terms of number of instructions. AVX3.2 increases the work done per instruction. This is the whole point of SIMD.

I dont want to get off topic here but AVX does increase IPC(InstructionS Per Cycle). What people here refer to as IPC is actually the CPI(Cycles Per Instruction).

 

[pw257008]

I dont want to get off topic here but AVX does increase IPC(InstructionS Per Cycle). What people here refer to as IPC is actually the CPI(Cycles Per Instruction).

If I/C changes, then so does C/I, one is simply the inverse of the other

 

[Ajay]

AVX3.2 does not change IPC! IPC = instructions per clock. Throughput in terms of number of instructions. AVX3.2 increases the work done per instruction. This is the whole point of SIMD.

AVX and SIMD are actually about throughput; which in this case is bytes consumed per instruction.

Unfortunately, at the moment, there is some information that implies AVX 3.x may not be in Skylake (I think mikk pointed this out in another thread). It may only be in enterprise server CPU and hence probably HEDT CPUs - and even then, we are not sure what future Xeons will have AVX 3.x aside from Knights Landing (Xeon Phi).

 

[NTMBK]

AVX and SIMD are actually about throughput; which in this case is bytes consumed per instruction.

Indeed This is what I was trying to convey by "work done per instruction". Number of elements processed at once.

 

[witeken]

AVX and SIMD are actually about throughput; which in this case is bytes consumed per instruction.

Unfortunately, at the moment, there is some information that implies AVX 3.x may not be in Skylake (I think mikk pointed this out in another thread). It may only be in enterprise server CPU and hence probably HEDT CPUs - and even then, we are not sure what future Xeons will have AVX 3.x aside from Knights Landing (Xeon Phi).

Are people really buying into this FUD, or do you have any credible rumors for this, because, as far as I know, this was just speculation. It takes literally less than 5 seconds to debunk this speculation:

Not convinced?

Claiming Skylake won't have AVX3.2 is like claiming Canonlake won't have smaller transistors.

Anyway, doesn't IPC just mean performance/clock?

 

[Homeles]

Anyway, doesn't IPC just mean performance/clock?

In a literal sense, no. Literally, it means instructions per clock (duh...). But yeah, a lot of people use it to describe perf/clock.

Unfortunately, at the moment, there is some information that implies AVX 3.x may not be in Skylake (I think mikk pointed this out in another thread). It may only be in enterprise server CPU and hence probably HEDT CPUs - and even then, we are not sure what future Xeons will have AVX 3.x aside from Knights Landing (Xeon Phi).

I think mikk's the only person on that boat. The area penalty of AVX-512 would be too large to leave disabled.

 

[NTMBK]

Anyway, doesn't IPC just mean performance/clock?[/QUOTE]

No, IPC is just how many instructions a processor can execute on average in a single cycle.

 

[IntelUser2000]

Instead, I think Skylake might be a quite nice upgrade. We already know AVX3.2 and some othe things, and I think 14nm (Broadwell) will push Core into the mobile markets, and Intel will also have Broxton, so I don't think there's an immediate need for yet another very mobile focused update.

Intel brought in some power saving features from Skylake to Haswell, which suggests another nice update in power reduction.

I think the gain will be better than Haswell did(just because Haifa team focuses on the CPU core, versus platform for the Oregon team), but maybe not too much.

 

[Ken g6]

I think mikk's the only person on that boat. The area penalty of AVX-512 would be too large to leave disabled.

I have a theory about what Intel should do about higher AVX sizes. I think they should make the IGP's shaders capable of doing AVX instructions. Then, instead of giving each core its own AVX logic, one or more shaders should be assigned to each core. Benefits would include power use, die size, and the ability to expand AVX practically without limit in the future. Pentiums, especially, could be made much smaller by giving them only enough shaders for minimal onboard graphics. This would tend to imply that all i3s would have better graphics than all Pentiums, though there could still be binned, fused-off versions too.

The main downside to this that I see could be the introduction of a large latency penalty on AVX instructions. Hopefully this could be minimized or worked around.

Edit: Oh, yes, my point was that Xeons built for onboard graphics would have AVX 3.2, but Xeons-E's might not.

And, of course, this is all pure speculation on my part.

 

[Ajay]

Indeed This is what I was trying to convey by "work done per instruction". Number of elements processed at once.

Duh Quoted the wrong post, sorry - you were correct.

 

[Homeles]

Intel brought in some power saving features from Skylake to Haswell, which suggests another nice update in power reduction.

Where'd you read that?

Oh, looks like C9/10 were pushed forward.