Intel Broadwell BDW-H delayed May 2015

[mikk]

Just noticed: isn't that 2+3e chip new? In the previous leak only Skylake had 2+3e SKUs and they are supposed to be -U chips, not -H BGA ones...

Yes this new and it would be a nice addition.

 

[TreVader]

Okay, so zero practical performance advantage for how much lower power? Trying to say that BayTrail has no advantage over the ARM competition would be the same as my saying that Haswell Y obliterates everything ARM has to offer without mentioning the fact that it has the same level of power delta as Baytrail does compared to performance-competitive ARM cores.

Bay trail loses to ARM cores on idle power consistently and also loses in GPU very very consistently. It has never come close to offering any across-the-board advantage over ARM.


That's what a "process advantage" is supposed to be. If there was one, then you'd see intel dominating mobile just like they dominate desktop. But it's all FUD. Intel is losing billions just treading water in mobile.

 

[Khato]

Bay trail loses to ARM cores on idle power consistently and also loses in GPU very very consistently. It has never come close to offering any across-the-board advantage over ARM.

How precisely are you defining a loss on idle power?

As for losing in GPU to ARM-based SoCs, what's new there? Because I doubt anyone will try to claim that the graphics Intel put into Baytrail is at all suited to the market it's being shoved into. A process lead can't make up for poor design choices. Seeing how well Merrifield/Moorefield with their PowerVR graphics do compared to the competition based on architectures of similar efficiency will give you a good picture of how the process technology actually compares.

 

[Fjodor2001]

To me your hypothesis doesn't make sense. As far as I can see, Core is a suitable architecture for higher clock speeds, and 14nm isn't worse in an way than 22nm, certainly not in a meaningful way that it makes Intel consider skipping Broadwell-K..

How do we know that for sure? Could they not e.g. have heat issues due to higher transistor density at 14 nm?

Has any info been published officially stating that the actual Intel 14 nm chips (i.e. not just transistors) are suitable for high clock speeds at the current state of their process tech?

 

[Fjodor2001]

If it was simply clock speed issues, they could just simply only release the lower clocked versions.

But would it really make sense to release a new desktop CPU generation where the top end chips initially were slower than the previous CPU generation? I would have a hard time imagining Intel would do something like that.

Also, note that they are in fact releasing the low frequency models first, but they are starting with the mobile CPUs where low TDP matters more than high clock speed and performance (compared to on desktop CPUs). Then they are gradually releasing CPU models with increasing frequency. I.e. first the Y model, next the higher frequency U models, then finally the highest frequency H/K-models at the end. All over a ~9 moths time span, which is an unusually long period.

I still think it's an economics issue more than anything else - that the anticipated cost savings of going to 14 nm is taking much longer to achieve than hoped. Obviously they need to get Broadwell-U and Y out this year so if it's close enough they will just suck it up; but everything else will just have to wait.

You mean it's an economics issue because they are still having yields problems, so the percentage of usable chips is too low? Or did you have something else in mind?

Would be very surprised if they end up skipping Broadwell-H and go straight to Skylake.

Yes, I agree from what has been communicated by Intel lately. But maybe they considered it previously due to problems reaching high clock speeds at 14 nm, but then they changed their mind and delayed the high frequency desktop Broadwell-K model for a long time (~9 months compared to Y model) instead of simply canceling it completely. Thereby they will have more time to perfect the 14 nm process so it will allow for higher clock speeds.

 

[shady28]

Intel's been shipping 22nm FinFETs since 2012 in massive volumes, worth multi-dozens of billion dollars. Doesn't sound FUD to me. Here's some proof:

Yeah and we see how much extra performance that offered. Except for low power / mobile applications, the 22nm Ivy Bridge was the most pathetic desktop chip launch Intel has done that I can recall. There are actually a (not insignificant) number of places where 32nm Sandy Bridge outperforms 22nm Ivy Bridge at the same clock.

 

[jj109]

Why do think a die shrink at the same frequency should give any more performance?

 

[Sweepr]

Ivy Bridge is around 4% faster per clock than SB, not bad at all for a Tick. That small IPC bump + 100MHz higher base clock and improved Turbo resulted in ~9.5% performance improvement compared to older SB parts. It's not like AMD did better with Kaveri anyway. Comparing the fastest models, brand new SR-based A10 7850K barely matches the old A10 6800K @ stock. Boring time for desktop users.

 

[witeken]

Bay trail loses to ARM cores on idle power consistently and also loses in GPU very very consistently. It has never come close to offering any across-the-board advantage over ARM.


That's what a "process advantage" is supposed to be. If there was one, then you'd see intel dominating mobile just like they dominate desktop. But it's all FUD. Intel is losing billions just treading water in mobile.

Have I just found a paradox in your post? You seem to explicitly claim that Intel has its desktop domination because of their process advantage ...This means that there really is a process advantage, unlike what the rest of your post says.

(Even if Intel is failing with their mobile products like you claim (they don't), then without a process advantage they would be failing even harder. Or put another way: a process advantage doesn't mean you automatically dominate the market, although the odds are after a few years they will.)

The subject of the thread is Broadwell, not Baytrail/Airmont/(whatever Intel is claling it this week)
-ViRGE

 

[witeken]

Yeah and we see how much extra performance that offered. Except for low power / mobile applications, the 22nm Ivy Bridge was the most pathetic desktop chip launch Intel has done that I can recall. There are actually a (not insignificant) number of places where 32nm Sandy Bridge outperforms 22nm Ivy Bridge at the same clock.

No problem, here's some more, although less scientific, proof:

 

[jpiniero]

You mean it's an economics issue because they are still having yields problems, so the percentage of usable chips is too low? Or did you have something else in mind?

I imagine everything deals with yield in the long run. Imagine if the yield was good enough they could release it but bad enough that they would have to drop a couple hundred mill on additional fab equipment to be able to have enough chips to do U/Y and the H models at the same time. Remember Intel cut their fabs from 4 to 2 for 14 nm.

 

[Homeles]

Yeah and we see how much extra performance that offered. Except for low power / mobile applications, the 22nm Ivy Bridge was the most pathetic desktop chip launch Intel has done that I can recall. There are actually a (not insignificant) number of places where 32nm Sandy Bridge outperforms 22nm Ivy Bridge at the same clock.

If you're going to try to make a point, you might want to ensure it's outside of the margin of error, and not safely nested inside.

 

[el etro]

Why do think a die shrink at the same frequency should give any more performance?

Will not give. Will give all the benefits of a newer and smaller node.

 

[shady28]

If you're going to try to make a point, you might want to ensure it's outside of the margin of error, and not safely nested inside.

I have no idea what your point is.

My point, since it clearly went right over your head (and since you apparently weren't reading this thread very closely), was that 22nm Ivy Bridge vs 32nm Sandy Bridge is an excellent example of how a process node shrink (like Broadwell) does not in any way guarantee any significant performance advantage or increase. There are quite a few posts (including one weak response) where people seem to point at process node technology improvements equating to raw performance improvements - it clearly does not.

 

[Ajay]

I have no idea what your point is.

My point, since it clearly went right over your head (and since you apparently weren't reading this thread very closely), was that 22nm Ivy Bridge vs 32nm Sandy Bridge is an excellent example of how a process node shrink (like Broadwell) does not in any way guarantee any significant performance advantage or increase. There are quite a few posts (including one weak response) where people seem to point at process node technology improvements equating to raw performance improvements - it clearly does not.

Physics and economics seem to be pointing devices towards better performance per watt. Intel could push physics the other way and get more performance, but then they'd wind up with the same problem as we have with 5 GHz Piledrivers, hot as hell and requiring liquid cooling or they could design even bigger cores, massive caches and quad channel memory and then a desktop CPUs would cost as much as an HEDT Extreme processor.

 

[Homeles]

I have no idea what your point is.

My point, since it clearly went right over your head (and since you apparently weren't reading this thread very closely), was that 22nm Ivy Bridge vs 32nm Sandy Bridge is an excellent example of how a process node shrink (like Broadwell) does not in any way guarantee any significant performance advantage or increase. There are quite a few posts (including one weak response) where people seem to point at process node technology improvements equating to raw performance improvements - it clearly does not.

Your "point" didn't go over my head -- it never took off the ground. Seriously, what is this:

There are actually a (not insignificant) number of places where 32nm Sandy Bridge outperforms 22nm Ivy Bridge at the same clock.

This has nothing to do with process tech at all. Even an amateur could tell you that. On top of that, of course they perform similarly -- it's virtually the same underlying uarch at the same clock speed. This is how integrated circuits work.

Take any chip with the same uarch, put it on a new process node, and run it at the same clock speed. They will all perform the same as their older siblings.

If this was your "point," I'm baffled as to why you thought it needed to be shared. Literally everyone here knows this, and that includes witeken, the person you directed your original comment at.

Physics and economics seem to be pointing devices towards better performance per watt. Intel could push physics the other way and get more performance, but then they'd wind up with the same problem as we have with 5 GHz Piledrivers, hot as hell and requiring liquid cooling or they could design even bigger cores, massive caches and quad channel memory and then a desktop CPUs would cost as much as an HEDT Extreme processor.

At least for Intel, the primary motivator has become reducing cost through increased density. For the past few nodes, Intel chose to pursue better transistor performance over cost, and its competitors often had significantly higher density at the same node, while having considerably worse performance. Both 14nm and 10nm feature more than doubled density. Intel's wisely recognized that the primary decider in OEM wins is cost, not performance, and they're acting accordingly.

Thankfully, at least for 14nm, this isn't coming with a performance hit. Performance is well in line with Intel's historic norms, while their cost/transistor is outpacing their historic norms.

 

[witeken]

I have no idea what your point is.

My point, since it clearly went right over your head (and since you apparently weren't reading this thread very closely), was that 22nm Ivy Bridge vs 32nm Sandy Bridge is an excellent example of how a process node shrink (like Broadwell) does not in any way guarantee any significant performance advantage or increase. There are quite a few posts (including one weak response) where people seem to point at process node technology improvements equating to raw performance improvements - it clearly does not.

Of course it does not. Moore's law, which is what the semiconductor industry is following with their process nodes, isn't a law for higher performance, nor lower power consumption, but purely an economical law: transistors consistently keep getting smaller, which reduces the cost per transistor, which allows Intel and any other foundry to put more of them together or pursuit higher margins.

But Moore's law doesn't live in a vacuum. There's also something called Dennard scaling, which states that if you reduce every feature of a transistor with a constant factor, the heat per area will remain constant. That means if you shrink a transistor and put 2x as much of them in the same area, as dictated by Moore's law, every transistor will will only consume half as much, and clock speeds (and thus total performance) will double as well.

This scaling, however, at least for the higher performance (clock speed) part of it, broke down once quantum mechanics came in, after which Moore's law again became just a law of economics. Since higher performance isn't achievable anymore (2x higher clock speed means 8x higher power consumption), people began focusing on efficiency, reducing the amount of leakage as much as possible. However, with more transistors (as a result of making them smaller) you can still do more things, such as improving the architecture, and that's where today's improvements come from, but not much because ILP only gets you so far.

For ICs that rely on parallelism, you can exploit both -- higher efficiency (from transistor innovations) and more transistors (Moore's law) -- to keep substantially improving performance (take one from both away, however, like will happen at TSMC's 16nm, and GPUs will have the same fate as CPUs).

Or simply put, for CPUs that have not yet maxed out single threaded performance per clock, performance keeps improving at about the same factor as new nodes improve efficiency (reduces power consumption).

 

[Idontcare]

At least for Intel, the primary motivator has become reducing cost through increased density. For the past few nodes, Intel chose to pursue better transistor performance over cost, and its competitors often had significantly higher density at the same node, while having considerably worse performance. Both 14nm and 10nm feature more than doubled density. Intel's wisely recognized that the primary decider in OEM wins is cost, not performance, and they're acting accordingly.

Thankfully, at least for 14nm, this isn't coming with a performance hit. Performance is well in line with Intel's historic norms, while their cost/transistor is outpacing their historic norms.

Their target market changed.

Previously the majority of their high-margin chips were going into products that were going to be plugged into the wall 24/7.

Performance was the premium the customers were willing to pay for, so the customer drove Intel's R&D decisions and rightly so.

But then Intel noticed a critical cross-over happen, >50% of their ICs went into mobile products (laptops at the time).

The customer wasn't looking for 5GHz 8-core laptop CPUs, they wanted 3GHz dual-core chips that could give them 8hrs battery life in a form factor that trended towards that of a tablet.

So what you see is Intel doing what Intel has always done, follow the money. And right now the customers with the money are saying "give us better battery life, or lighter products because less weight goes towards the battery, at the expense of super-duper 10GHz performance".

And so you have R&D managers directing their teams accordingly. If the customers weren't voting with their wallets in this fashion then you could have counted on Intel's 14nm and 10nm nodes being more of the same in terms of higher and higher fmax targets while targeting flat-changes in TDP profiles (mainstream would have stayed at 105W TDP for example).

 

[witeken]

Thankfully, at least for 14nm, this isn't coming with a performance hit. Performance is well in line with Intel's historic norms, while their cost/transistor is outpacing their historic norms.

Honestly, I think Intel's just making up for the weak (~1.7x) density increase at 22nm. Everyone can see that the extra bonus of 14nm isn't really a bonus at all seen over the long run:

Over the course of 7 succeeding process nodes, 10nm will be off by roughly a factor of 2; from 130 to 10nm should result in a scaling of 169 as opposed to less than 100.

Edit: now that I look at this slide, I wonder how accurate it is, because I don't see the recessed 22nm density improvement reflected in it, they all look kinda the same. But the point that 14 and 10nm are making up for 22nm remains true, and is in fact even better illustrated by the numbers from another slide, which confirm 32->22 is exactly 8x higher density.

 

[Idontcare]

Edit: now that I look at this slide, I wonder how accurate it is, because I don't see the recessed 22nm density improvement reflected in it, they all look kinda the same. But the point that 14 and 10nm are making up for 22nm remains true, and is in fact even better illustrated by the numbers from another slide, which confirm 32->22 is exactly 8x higher density.

Remember you are looking at one thing (intrinsic density capability on the basis of design rules and the PDK) while trying to compare with another thing entirely (final xtor density as designed by the layout engineers when creating products that are optimized for something other then peak absolute density).

Just because Intel's process node development engineers make it feasible for 32nm->22nm to scale as much as 45nm->32nm could, doesn't mean the IC design engineers elected to push the limits all the way in terms of allowed design rules to capture 100% of the density entitlement.

There will be a lot of other design considerations in the process which can steer the design towards a less dense layout, clockspeed targets and hotspot avoidance being two of the biggies.

And so we have to be cautious about looking at what Intel is saying in that middle graph regarding mm2/xtor and what 14nm and 10nm will bring over that of traditional density scaling.

Just because the nodes will enable vastly superior xtor densities doesn't mean the products made on those nodes will themselves have crazy high density, just means they could have if the IC design teams elected to take advantage of the farthest scaling extremes allowed by the node's design rules (at the expense of something else electrically, be it clockspeeds or thermal density, etc.).

So, believe the marketing slides, no reason for Intel to lie about it. But be careful in how you project from intrinsic capability of the node to what the final products are going to have been optimized for. Things like Quark will probably push their density to the limits allowed by the design rules, things like fast sram cache and 4GHz big cores probably will stay well above those density entitlements.

 

[witeken]

Thanks, that makes a lot of sense. But I have 1 remark: your assumption is that Intel is putting theoretical mm²/transistor density in those slides. However, Intel's slide is made to give us a view of the historical price/transistor trend and how it will go for Intel in the future. Intel can't really do anything with theoretical margins, so this slide would be pretty useless if it didn't tell anything about reality.

Now that I read Homeles' post again, it seems that I actually jut confirmed what he said by showing that slide ; they're outpacing their own historic cost/transistor norms, not Moore's law's dictated density norms.

 

[Ajay]

Thanks Homeles, IDC & witeken - this thread just became awesome :thumbsup:

 

[Idontcare]

Thanks, that makes a lot of sense. But I have 1 remark: your assumption is that Intel is putting theoretical mm²/transistor density in those slides. However, Intel's slide is made to give us a view of the historical price/transistor trend and how it will go for Intel in the future. Intel can't really do anything with theoretical margins, so this slide would be pretty useless if it didn't tell anything about reality.

Intel has always made more than one IC on any given node, are you trying to make the argument that all of Intel's IC's had the same xtor density? Think about it, surely it can't be an average value of all their IC's (how do they weight the average then without creating a still useless "theoretical margins" numbers? it would have to be an average weighted by sales volume of each IC and that is way too complicated an effort to go to for a single marketing slide, but design rules are readily available numbers from the PDK)

There is only one value that makes sense to put into a graph, the entitlement value. Entitlement is a big word in node development, it is the focus of the management team from the beginning of every node that goes into development.

I am not making the assumption they are putting theoretical mm2/xtor in the graph, there is nothing theoretical about it. To be sure they are putting actual spec'ed design rule minimum values in the graph, there is no reason not to.

Now that I read Homeles' post again, it seems that I actually jut confirmed what he said by showing that slide ; they're outpacing their own historic cost/transistor norms, not Moore's law's dictated density norms.

That is absolutely true, and is the part that makes Intel at 10nm extremely dangerous to any company that is a competitor whenever Intel's 10nm products hit the market. It is a game changer opportunity for Intel.

 

[Homeles]

That is absolutely true, and is the part that makes Intel at 10nm extremely dangerous to any company that is a competitor whenever Intel's 10nm products hit the market. It is a game changer opportunity for Intel.

It certainly is. Intel has the ability, as an IC design firm with its own fab, to undercut its competition while still maintaining fat margins. They haven't been leveraging that -- they've been using relatively high cost designs and selling them for a lot.

Intel's potential advantage, now that they're playing the cost game, can rather simply be shown through a bit of algebra. If an IC costs $1 to produce, the fab will want to sell it with a 30% margin (sometimes more, sometimes less). So the cost to the fabless company in this example is $1.30. They'll want a 30% margin of their own, which is multiplicative, and thus the final price to the OEM is $1.69.

Intel on the other hand likes their 60% margins. Their IC costs $1.00 to make as well, but they can sell their IC for their desired $1.60 and still come ahead.

Fabless model:
Base cost * foundry margin * fabless semico margin = final selling price

"Fab-full" model:
Base cost * margin = final selling price

This is ignoring yield, which would affect both models (perhaps it would affect one worse than the other, but I'm feeling too lazy to think about it). The numbers are obvious made up too, but hopefully my point is easy to see.

I am not making the assumption they are putting theoretical mm2/xtor in the graph, there is nothing theoretical about it. To be sure they are putting actual spec'ed design rule minimum values in the graph, there is no reason not to.

Right, they're undoubtedly quoting their minimum 6T-SRAM cell cize. For 22nm, Intel offered low power and high performance SRAM styles as well, which were less dense. I'd imagine those wouldn't scale as well.

I've read that SRAM scaling is running into a bit of trouble, at least for some of the other foundries. It seems that it's caused, at least in part, by the lack of EUV. It's a shame that, despite the promise that SRAM replacements promised, nothing has surfaced thus far. SRAM caches are such a critical component of an IC's performance... an improved technology would be a big breakthrough.

 

[shady28]

It certainly is. Intel has the ability, as an IC design firm with its own fab, to undercut its competition while still maintaining fat margins. They haven't been leveraging that -- they've been using relatively high cost designs and selling them for a lot.

...

Net income Margins of Qualcomm vs Intel :

2013 -

QCOM :
Revenue : 24,866,000
Net Inc : 6,853,000
Net Inc : Revenue = 27.5%

INTC :
Revenue : 52,708,000
Net Inc : 9,620,000
Net Inc : Revenue = 18.3%

Moreover, Qualcomm experienced 25% revenue growth in 2013 vs 2012 while Intel's revenue declined about 1%.

So using your logic, QCOM should go out and start buying Fabs. So should apple, etc.

I don't see that happening. These companies do well by focusing on what they are experts at, not by attempting to own all aspects of production. Inevitably companies that do that become "mediocre" at everything, which is really what I think is happening to Intel. Their tick/tock is producing less and less interesting chips with longer and longer cycle times.