No, this was just announced yesterday, it's quite new. It is pretty exciting in that we should be able to see shrinks using current techniques for the next 5 years or so, after that we'll be hitting physical limits pretty badly.
There are a few things I want to point out:
First, the 20% transistor performance benefit is both from a shrink AND these new materials. Also, transistor performance does not translate into a linear increase in chip performance, so I'd expect maybe 10-15% chip performance (max clock potential, basically) at most.
Secondly, there's 80% less current LEAKAGE. Leakage is the power draw when a transistor is switched off, basically it never is completely switched off, there's always a trickle going through. Ideally this should be zero (it's also close to impossible, and I say close in case there's some crazy manufacturing technique I've never heard off) and this is not the same as dynamic current, which is the current draw when a transistor is switched on. Also, it's not 80% across the board, I'd say expecting a 50% drop in leakage current is being generous, I'd expect power draw to drop around 5-10W at idle just because of this reduction. Of course, the 65nm shrink and the new metal gates should lower dynamic power quite a bit, too.
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