Intel and AMD FSB speeds and memory speeds...

[imported_Dynamite]

I just want to know if this is correct...

AMD's official bus speed is 400Mhz and Intels is 800MHz

For AMD: The ram is 200MHz DDR which provides an effective 400MHz for the CPU.

For Intel: The ram is 200MHz DDR - How does Intel manage to read the signal 4 times as quickly? I understand reading on the rise and fall of the cycle. Do they manage to do this twice every clock?

I've also noticed that now AGP/PCI and PCI-E frequencies can be fixed to not change with the memory speed.

How do they mange to do this?

I know the CPU's frequency is directly tied to the FSB.

 

[imported_Dynamite]

Nobody can answer my question?

 

[alimoalem]

i thought the socket 754 was 1600MHz FSB and the 939 is 2000MHz

 

[bladephoenix]

That's my understanding. I thought that AMD64 has a memory bandwidth of 6.4 GB/s, which translates into dual channel DDR 3200 @ 400 Mhz each channel. Intel is similar in that its FSB is 800 Mhz, which is equated by two DDR 3200 @ 400 Mhz working in dual channel (2 x 400 Mhz = 800 Mhz), which is again, 6.4 GB/s.

 

[ViRGE]

Your definitions are a bit out of date, Dynamite. For modern processors:

Intel: You're largely right here. Intel pumps the bus 4 times a cycle, twice on the rise and twice on the fall.

AMD: This is a bit harder to explain. With AMD's setup, they no longer have a traditional FSB setup, instead they have what's called Hypertransport. The big difference here is that CPU-RAM communications are no longer related to CPU-Northbridge communications, so when we're talking about Hypertransport, we are talking solely about CPU-NB. The details of how HT work are unimportant, all you need to know is that it operates at either 1600mhz or 2000mhz, 16bits wide, and other clocks(such as the RAM clock) are derived from it. As for interfacing with the memory, AMD's memory interconnect has no real name, it's really just a physical link between the RAM and CPU, there's no funny business going on.

Fixed Frequencies: Basically they buffer communications, such asynchronous operation is a PITA to make work.