Originally posted by: Viditor
A lot of hypotheticals there...
1. Intel will almost certainly NOT use IA64 for the desktop. The conversion to EPIC and vastly reduced x86 speed are the main reasons that Itanium sales remain quite dismal.
And that most desktop apps are very much not parallel, where many many many many server apps are, so even if you could get over the emulation thing, most apps would need to be rewritten.
2. Based on lead times required, it's inconceivable that Intel will have an x86-64 CPU before Tejas. Given that, it will probably be multi-core, SOI, and 65nm (as will AMD's K9, due out near that time as well).
However, if they have 64-bit address space on the way anyhow, they might be able to make some instruction converter of some kind (arg...I know there is a nice word for that), and basically add the registers and such, then tack the hardware emulator whatever (after this post I'm googling for a bit on that!), and go for it. If they had 64-bit on the way and it was IA64...yeah, nothing until then.
3. As Tejas will be the next generation, there are even more questions...
a.) Will it use Hypertransport? (they are licensed to use it...)
Seems a prestige thing for them not to use it
for the CPU's bus.
b.) Will it have an onboard memory controller?
They used the i850 mess to show why they weren't bothering, and they have good performance without it. I wouldn't be at all suprised if the whole long pipeline thing helps make up for it and gove the memory controller time to do its job, where AMD is heavy on speedy branching. Know any good places to read up on such things?
c.) Will they increase the Trace Cache?
Why not? if it is needed, they will

.
IMHO, there is far too little info available to answer the questions...
We probably won't have even a glimmer of an idea for at least 12-18 months...
Nope. I'd hate to be one of their engineers in that stuff...having the tech for years in advance and keeping my mouth shut.