Originally posted by: wwswimming
i don't know how it works for Hi-K and other semiconductor materials.
for many materials, voltage standoff is roughly proportional to thickness.
for Kapton (polyimide), voltage standoff for the first mil (.001 inch)
is about 5 KV, then slowly decreasing. after about .005, voltage standoff
is about 3 kV per mil. that's an insulator, not a semi-conductor.
i wonder what the standoff numbers are for semiconductor materials.
also, if voltage 'fatigue' is anything like mechanical stress fatigue, where
you add up numbers of cycles at different stress levels using something
called Miner's Analysis.
The Hi-K (for insulating the drain from the gate) as well as low-k (for insulating line-to-line) dielectrics serve the exact same purpose and the concepts are identical.
The vocabulary differs of course as is common with all industries, but the physics and mathematics are identical (when
properly applied).
To ascertain whether Intel's specific implementation of their 45nm materials, integration, and design rules render the CPU's of said node any more or less susceptible to electric field induced defect mechanisms than their 65nm node one must
first account for the obvious differences in design rules first and formost.
A 65nm node with critical metal pitch of 180nm (90nm dielectric spacer, 90nm metal line) versus a 45nm node with critical metal pitch of 140nm (70nm dielectric spacer) simply cannot support the same absolute voltage or changes in voltage because of the obvious dielectric spacer change...unless the dielectric material is improved commensurate with the electric field increase.
This is but one of the many many reason operating voltage is reduced node-on-node from prior nodes.
No one can answer the question of whether Intel's 45nm process tech is more/less susceptible to electric field induced degradation (once the voltage has been normalized so as to normalize the electric field) compared to their 65nm process tech
except Intel...and you can be sure they do know the answer as this is routinely and robustly characterized and optimized during the node development cycle well before production starts.
For us hacks, the typical enthusiast consumer who doesn't know jack about process technology let alone standard electric field effects, the least we could do is use the rule of thumb that operating voltage tolerance ought to be scaled by the skrink factor...45nm/65nm = 69%...so we should not expect our 45nm Intel chips to survive beyond a 69% voltage increase relative to the kind of voltage increase we expected our 65nm Intel chips to survive (this is just simple electrical engineering, no rocket science here).
So if your 65nm Q6600 with a VID of 1.3V was expected to survive a 0.3V overvolt (i.e. overvolted to 1.3+0.3 = 1.6V) you should not expect your 45nm Q9450 with a VID of 1.1V to survive a 0.3V*0.69 = 0.2V over-volt.
In other words, putting your Q9450 at Vcore of 1.1V+0.2V =
1.3V ought to be considered just as much of an "over-voltage" as putting your Q6600 at a Vcore of 1.6V.
Go above 1.3V on your Q9450 and expecting it to survive is about the same as putting more than 1.6V on your Q6600 and expecting it to survive...and this is just scaling the voltage for electric field induced degradation issues, no mystery here.