Intel 22nm v.s. TSMC 16nm

[Arachnotronic]

Hi all,

So, at IEDM 2012, Intel presented the following performance numbers for its 22nm SoC process:

At IEDM 2013, TSMC gave the following Idsat (NMOS/PMOS) number at the same voltage at 30 pA/um leakage: 520/525 uA/um

In the same paper, they claimed that "normalized speed" increase of 16 FF over 28nm HKMG was >35% at the same power and >55% lower power at the same performance.

Unless TSMC 28nm HKMG was just as fast as Intel 22nm FinFET, something's not right here. What is the missing piece of this puzzle?

My understanding is that these Idsat numbers are meaningless without knowing the gate capacitance (since we ultimately care about switching speeds) because the ultimate measure of performance is switching speed, so if you have much higher gate capacitance coupled with your high drive current, the increase in drive current isn't necessarily the increase in your switching speed.

(disclaimer: I am not an EE)

Any insights/input would be appreciated!

 

[witeken]

First reaction when I saw the title: "LOL, is he still confused about the companies' process nodes, so he made a second thread."

This time it seems to be about factual data, though. Unfortunately, I can't help you at this moment.

 

[Homeles]

TSMC's LP 28nm numbers were (at .8V) were 700@100ua/um NMOS and 400@100ua/um PMOS. Just providing numbers for reference... don't have the time to number crunch right now.

http://www.realworldtech.com/includes/images/articles/iedm10-10.png?71da3d

 

[OCGuy]

I wouldn't read too much into PR performance claims from any company. We have seen too many times that they are either cherry-picked or outlier situations. Although it would be better if you could link to these claims, since many of us played the "telephone" game as kids.

I don't think TSMC could achieve that regarding "normalized" performance, when their website claims the following for 20nm, which is 16nm minus FinFETs)

TSMC's 20nm process technology can provide 30 percent higher speed, 1.9 times the density, or 25 percent less power than its 28nm technology.

http://www.tsmc.com/english/dedicatedFoundry/technology/20nm.htm

The way I read it is that in order to achieve the higher speed, you give up the power savings.

Overall performance is obviously up to the client's design, as 1.9x density could exceed 30%.

 

[zlatan]

You should read some new paper about Dennard scaling. It will help you to understand what happening.

 

[Homeles]

I wouldn't read too much into PR performance claims from any company. We have seen too many times that they are either cherry-picked or outlier situations. Although it would be better if you could link to these claims, since many of us played the "telephone" game as kids.

I don't think TSMC could achieve that regarding "normalized" performance, when their website claims the following for 20nm, which is 16nm minus FinFETs)



http://www.tsmc.com/english/dedicatedFoundry/technology/20nm.htm

The way I read it is that in order to achieve the higher speed, you give up the power savings.

Overall performance is obviously up to the client's design, as 1.9x density could exceed 30%.

I've not really seen any damningly false performance claims from any vendor. You just have to understand that when they say "up to," you really don't ever get that much on average.

Here though, these are the published process specifications. They definitely could be manipulated, but historically those numbers have been truthful, or at least truthful enough to be in line with real world observations. For example, when Chipworks put Ivy Bridge under the microscope, they found that its SRAM density was what Intel had claimed. Also, if you look at IBM's PDSOI at 45nm vs 32nm, you can see that 32nm wasn't much higher performing than 45nm, just as their published ldsat/off numbers show. When ldsats, minimum cell densities, operating voltages, etc. are published at these conferences, they tend to be accurate. At least from my observations.