Chew on this for awhile.
http://www.amdzone.com/index.p...finfet-sram-cell-with-
Than there is this.
http://www.tomshardware.com/ne...-transistors,2927.html
Than this one.
http://www.semiconductor.net/a....html?industryid=47298
Ireally don't know what the Intel fellow is talking about . But It looks like smoke and mirrors to me.
From Toms
Intel is going to great lengths to get a better handle on the power consumption of its semiconductors.
On step closer to reality is the "tri-gate" transistor, which enables the company to gain more flexibility in adjusting, processor performance and power consumption. The technology could be available by 2009 and drop a chip's total power by 35%, Intel said.
The tri-gate transistor isn't entirely a new announcement, as the company has been talking about the technology at various events since September of 2002. Presenting at the 2006 Symposia on VLSI Technology and Circuits in Honolulu, Hawaii, Intel followed up with more details and first test results, which indicated that the tri-gate transistor, often also referred to as "3D transistor" may in fact be a technology that will make it into production one day.
Intel's approach to enhance the gate technology in transistors tackles one of the major concerns especially in micro processors. Transistor gates consist of a gate electrode and gate dielectric. Both components control the flow of electrons between the source and drain by switching on and off the main current. Shrinking the structures of transistors has created several challenges such as increasing current leakage in "off" states of a transistor - causing the overall power consumption of a semiconductor device to climb.
While Intel has found solutions to keep the traditional gate architecture alive through the introduction of strained silicon to enhance electron flow and a so called "high-K" gate material in place of silicon dioxide to reduce current leakage, additional shrinks may require completely new approaches to control leakage and improve transistor performance. One possible solution could be tri-gate transistors, Intel believes.
Compared to today's planar transistors, tri-gate transistors use three gates instead of only one. According to Mike Mayberry, vice president and director of component research at Intel, the addition of two gates allows the company to increase the amount of current running through the transistor and decrease leakage since current can be routed into three different channels. First tri-gate transistors apparently have been manufactured and Mayberry claimed that 65 nm versions offer a 45% increase in speed or 50x reduction in "off"-current when compared to regular planar transistors.
If Intel can transfer these numbers into greater amounts of transistors, it isn't hard to imagine that tri-gate technology will become more and more important over time: With the amount of transistors doubling every 18 - 24 months and a growing flexibility to turn more parts of a micro chip on and off, a 50% reduction of off-current could deliver a whole new range of mobile devices and bring us closer to those notebooks with 8 hours battery time.
An even better solution than tri-gate transistor would be a pipe-structure, with a single gates and completely surrounding the electron flow from source to drain. However, this would require Intel to create a "tunnel" for the main current, which - according to Mayberry - is still science fiction. "At least today we cannot manufacture such a model," he mentioned in a conference call. However, he did not rule out that future technologies could provide an opportunity to develop such a transistor.
The executive stressed that tri-gate technology is "only one" approach to control performance and leakage in production processes down the road. But even if tri-gate is barely more than a research project - Mayberry said that Intel is "nowhere near to build 1 billion tri-gate transistors onto one chip - it appears to make steady progress and not be one of Intel's countless research projects that don't make it past a scientific paper presentation.
Mayberry indicated that a mass-production of the tri-gate transistor would be possible "with the 32nm chip generation," which is expected to debut at the end of 2009. If adapted, he expects the technology to move across all semiconductor products built by Intel.
It's not increased performance at any cost, it's increased performance at approximately equivalent cost per wafer. The most luxurious of cost increase budgets I have seen (industry-wide) for commodity CMOS nodes is 30% for node-over-node cost increase per wafer. 20% is more the norm/target.
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