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Discussion Intel’s Unified Core

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DavidC1 said:
I don't know where people got the idea caches are power or area inefficient. It is a "dumb" way of adding performance.
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I'm not claiming that caches are power inefficient, but they definitely can be less area efficient than adding more cores. That's why Zen5c halves the L3 cache.
 
Covfefe said:
I'm not claiming that caches are power inefficient, but they definitely can be less area efficient than adding more cores. That's why Zen5c halves the L3 cache.
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I'm responding to @Geddagod's claims that having large private caches is somehow a bad thing. That's why we DON'T include caches in our calculation, because it's the easiest thing to add(except L1). It's close as to copy paste as you can get.

If you are going to add anything, then first you have to consider whether it'll be better than adding cache. But the area efficiency argument is also not straightforward either, because it's extremely redundant. It's a sea of redundancy, that's why the cache portion of the die shots are so smooth.
 
DavidC1 said:
I'm responding to @Geddagod's claims that having large private caches is somehow a bad thing.
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It eats up a bunch of area, and Intel needs it to compensate for a bad uncore. This isn't an added bonus.
DavidC1 said:
That's why we DON'T include caches in our calculation, because it's the easiest thing to add(except L1). It's close as to copy paste as you can get.
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Ur right, lets not include caches. It doesn't take up space on the die, those giant cache blobs are actually just figments of our imaginations.
DavidC1 said:
But the area efficiency argument is also not straightforward either, because it's extremely redundant. It's a sea of redundancy, that's why the cache portion of the die shots are so smooth.
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No, it's pretty straight forward. Even if it doesn't hurt yields as much, that space is still being missed out for stuff like wider cores or just outright more cores. And it only gets worse and worse as logic scales better than SRAM with newer nodes.
There's a reason why entire cache layers (infinity cache MI300, L3 clearwater forest) are being moved off the compute tile. Cache eats up a bunch of space needed on the compute tile for other stuff.
DavidC1 said:
So this isn't necessarily accurate analysis either. There's a saying "before you expand your uarch, consider if it'll be worth adding equivalent amount in caches instead".
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The leading edge designs in ARM cores have very area consuming cores in terms of logic, with smaller shared caches. The leading edge design in x86 has "skinny" cores with a very fast L3.
In Intel's case, maybe for LNC they need those extremely large private caches, but that's just a result of L3 being bad and mem latency being relatively even worse vs the competition.
Covfefe said:
I'm not claiming that caches are power inefficient,
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Yeah, no one has ever claimed that lol, idk where that strawman is coming from.
DavidC1 said:
Delays happen not to "make it better" but because they mis-fired and needed extra time to fix things.
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Not when things get redefined. Like GNR.
DavidC1 said:
So a hypothetical CWF last year could have been 15% better perf/watt while arriving more than 6 months earlier.
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How?
DavidC1 said:
The same with Clearwater Forest arriving 3-5 months ago and performing 10-15% better. It would also have been a big impact.
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Sure lol? Idk what your point with this is.
 
Geddagod said:
Not when things get redefined. Like GNR.
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redefinition adds delay
Geddagod said:
No, it's pretty straight forward. Even if it doesn't hurt yields as much, that space is still being missed out for stuff like wider cores or just outright more cores. And it only gets worse and worse as logic scales better than SRAM with newer nodes.
There's a reason why entire cache layers (infinity cache MI300, L3 clearwater forest) are being moved off the compute tile. Cache eats up a bunch of space needed on the compute tile for other stuff.
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also cost cause cache per sq. mm2 is not improving much when compared to logic improvement
 
I tried putting this link into the forum search but couldn't find it, so...

US20250217160A1 - Software defined super cores - Google Patents

Techniques for software defined super core usage are described. In some examples, in super core mode each of a first processor core and a second processor core is to include circuitry to support the first and the second processor core to operate in a single virtual core as configured by the...
patents.google.com
 
soresu said:
I tried putting this link into the forum search but couldn't find it, so...

US20250217160A1 - Software defined super cores - Google Patents

Techniques for software defined super core usage are described. In some examples, in super core mode each of a first processor core and a second processor core is to include circuitry to support the first and the second processor core to operate in a single virtual core as configured by the...
patents.google.com
Click to expand...
It's not part of Intel Unified Cores though
 
soresu said:
I tried putting this link into the forum search but couldn't find it, so...

US20250217160A1 - Software defined super cores - Google Patents

Techniques for software defined super core usage are described. In some examples, in super core mode each of a first processor core and a second processor core is to include circuitry to support the first and the second processor core to operate in a single virtual core as configured by the...
patents.google.com
Click to expand...

This forum still has a search? It feels straight out of the 90's. "Actively working on a resolution" My ass.
 
So this is 3rd future gen CPU right. After Nova and Razer. I wonder how the market would be at that point. If AI frenzy is down, I feel a global recession could put a kibosh on plans. If frenzy is still there, then we will still be stuck with DDR5 as DDR6 would be too expensive for client 🙂 Already rumors next year is only minimal phones would use LPDDR6 as its too expensive. Plus one Chinese OEM is bailing out of Ultra phones as its too expensive to manufacture.
 
511 said:
Yes but as i said Unified is just a brand new Core uArch all together led by Stephen Robinson
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It is really a bit boring compared to Royal Core. Royal v3 + copper shark titanlake looks great, 300% Golden Cove IPC is ST king. Current x86 ST looks lame compared to Apple.
 
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