Discussion Intel’s Unified Core

[adroc_thurston]

And E cores have consistently done much more dramatic changes for the past decade without regressions

Kind of?
The two big shifts were Silvermont (yay OoO) and Tremont (the start of them aiming at way higher perf).

 

[poke01]

More dense by what, single digits?
And a worse yielding, lower perf node. N3E is outright the better node.

N3B is dense. M3 P core is 2.49mm2 and M4 P core is 2.97mm2. Just the cores, no shared caches. M2 is 2.76mm2.

Make of that what you will. Though with Panther lake will the P core increase in size?

Will be interesting to watch for

 

[511]

N3B is dense. M3 P core is 2.49mm2 and M4 P core is 2.97mm2. Just the cores, no shared caches. M2 is 2.76mm2.

Image of that what you will. Though with Panther lake will the P core increase in size?

Will be interesting to watch for

Cougar cove has a size decrease from N3B to 18A also N3B vs N3E is only 1.04x denser.

 

[Geddagod]

N3B is dense. M3 P core is 2.49mm2 and M4 P core is 2.97mm2. Just the cores, no shared caches. M2 is 2.76mm2.

I've gotten slightly larger numbers for Apple's cores (except for the M2), but those are pretty much within 5% of what I got.

Though with Panther lake will the P core increase in size?

Rumored to be smaller actually.

 

[igor_kavinski]

Cougar cove has a size decrease from N3B to 18A

They would be able to do better DTCO with their own process than TSMC's process anyway I think. Using TSMC is probably something they begrudgingly accepted and not really keen on doing if they could have a say in the matter. I bet internally they are blaming TSMC N3B for their own design failures.

 

[Kepler_L2]

They would be able to do better DTCO with their own process than TSMC's process anyway I think. Using TSMC is probably something they begrudgingly accepted and not really keen on doing if they could have a say in the matter. I bet internally they are blaming TSMC N3B for their own design failures.

Not at all, CCG wanted to move away from Intel nodes.

 

[LightningZ71]

Cougar cove has a size decrease from N3B to 18A also N3B vs N3E is only 1.04x denser.

Most of the density difference between the two nodes is SRAM related. N3E relaxed SRAM density as compared to N3B to the point that it barely scales from N4P.

 

[igor_kavinski]

Not at all, CCG wanted to move away from Intel nodes.

Ironically then Arrow Lake is a big oopsie moment for them.

I wonder how many people internally pointed their fingers at them, all the while holding their aching bellies and laughing.

 

[igor_kavinski]

N3E relaxed SRAM density as compared to N3B to the point that it barely scales from N4P.

But N3B's denser SRAM has performance issues, no? How else did Arrow Lake get saddled with slow as molasses L3?

 

[511]

Not at all, CCG wanted to move away from Intel nodes.

That's a political decision as well don't forget this politics has been going on for years.
Also the DTCO is real for Intel design on Intel nodes Intel nodes external and Internal PDK has difference due to DTCO.

 

[511]

But N3B's denser SRAM has performance issues, no? How else did Arrow Lake get saddled with slow as molasses L3?

Intel F***** the design of SoC+Ring that's why LNL is perfectly fine.

 

[Kepler_L2]

That's a political decision as well don't forget this politics has been going on for years.
Also the DTCO is real for Intel design on Intel nodes Intel nodes external and Internal PDK has difference due to DTCO.

The story is that CCG got frustrated being held back by 14nm+++++++ and then 10nm+++++++ but Murthy Renduchintala didn't want to move anything to TSMC. Jim Keller on the other hand wanted the design teams to have freedom to use whatever node they felt was best (and also wanted Intel to abandon their internal tools and use industry standard EDA stuff) and managed to convince Bob Swan to give more freedom to CCG.

Everything Arrow Lake onwards was going to be on TSMC, but Jim Keller left due to political infighting with Murthy and others. When Pat took over they started to move some stuff back to Intel foundry.

 

[511]

The story is that CCG got frustrated being held back by 14nm+++++++ and then 10nm+++++++ but Murthy Renduchintala didn't want to move anything to TSMC. Jim Keller on the other hand wanted the design teams to have freedom to use whatever node they felt was best (and also wanted Intel to abandon their internal tools and use industry standard EDA stuff) and managed to convince Bob Swan to give more freedom to CCG.

I know about this part but their was some politics in CCG as well to not move it to TSMC there was lots of political fighting between CCG/Foundry and inside CCG as well for this also when the fab was dominating nobody at Intel including CCG wanted to give the world access to foundry lol.

Bob Swan was planning to Can the entire Fabs after 1-2 node he took it to extreme and the same decision is costing them issues rn as well don't forget people are buying RPL due to It is more expensive to buy ARL/MTL TSMC delay of N3B didn't help as well.

I agree with the Jim Keller's though about CCG and Foundry and in the end when Pat took over he did both.

pat took the right decision for foundry and design. Volume in fabs while designing SKUs and design to stop doing what they have been doing but the plan was to reduce external dependency to near zero in future which got changed when MJ/DZ took over and now I don't know the current status.
The main issue is they are jumping around instead of fixing their freaking strategy. I want to know LBT's strategy

 

[LightningZ71]

But N3B's denser SRAM has performance issues, no? How else did Arrow Lake get saddled with slow as molasses L3?

On a very basic level, yes. N3B is a best-effort scaling node. N3E is a "What can we do to N3B to make it perform at least as well as N4P?" N3P is a "This is what we can do with more time to fine tune all of N3 and give you something that is clearly better than N3P.

Arrow Lake is stumbling because Intel didn't resolve all of the fabric/on package network issues from Meteor Lake before freezing the Arrow Lake design.

 

[igor_kavinski]

I want to know LBT's strategy

Fire senior employees. Ask the young ones, "Now's your chance to do better!".

Or will he do the opposite?

 

[Geddagod]

Bob Swan was planning to Can the entire Fabs after 1-2 nod

Source?

and the same decision is costing them issues rn

Like what?

as well don't forget people are buying RPL due to It is more expensive to buy ARL/MTL

Tariffs, and because ARL and MTL offer no significant ST perf improvement.
Battery life seems to be pretty much the only thing keeping ARL moving.

TSMC delay of N3B didn't help as well.

Which didn't impact Intel at all.

 

[511]

Source?

Trust me Bro

Like what?

outsourcing 100% of everything to TSMC without accounting for Internal vs External

Tariffs, and because ARL and MTL offer no significant ST perf improvement.
Battery life seems to be pretty much the only thing keeping ARL moving

Price Matters as well

Which didn't impact Intel at all.

Oh really it did affect them on already delayed schedule

 

[Geddagod]

outsourcing 100% of everything to TSMC without accounting for Internal vs External

They very clearly did not outsource everything to TSMC.
Also, Intel did not just slap TSMC 20A onto ARL last second and call it a day. If not from conception, ARL was planning to keep a decent amount of dies internally, early into development.
Also Internal vs External strategy can only last so much longer. Continuing bleeding edge node development is only getting more expensive. The fabs can realistically bankrupt the company.

Price Matters as well

Price only matters because Intel can't have ASPs too high because ARL is mediocre, and LNL has MoP margin % issues.
And regardless of what node Intel uses, last gen products will always have lower prices, and so Intel will always be selling more older skus in this environment due to tariffs.

Oh really it did affect them on already delayed schedule

It didn't.
Apple launched N3B products well before Intel did.
And ARL launched in lock step with MTL, it was the knockback effect of MTL delays that pushed everything back for Intel, not TSMC N3B delays.

 

[511]

They very clearly did not outsource everything to TSMC.
Also, Intel did not just slap TSMC 20A onto ARL last second and call it a day. If not from conception, ARL was planning to keep a decent amount of dies internally, early into development.
Also Internal vs External strategy can only last so much longer. Continuing bleeding edge node development is only getting more expensive. The fabs can realistically bankrupt the company.

They did in 2021 after pat joined the foundry roadmap was redefined with ARL moving few SKU to 20A. ARL's original definition was sometime in 2020 with N3 when swan did Prepay and i agree with the last part.

Price only matters because Intel can't have ASPs too high because ARL is mediocre, and LNL has MoP margin % issues.
And regardless of what node Intel uses, last gen products will always have lower prices, and so Intel will always be selling more older skus in this environment due to tariffs.

ARL-H/HX are not mediocre unlike S

It didn't.
Apple launched N3B products well before Intel did.
And ARL launched in lock step with MTL, it was the knockback effect of MTL delays that pushed everything back for Intel, not TSMC N3B delays.

N3B had 6 month delay and combined with Intel's own delay things got pushed out quite a bit also MTL was delayed the moment d 7nm got delayed original 7nm was canned like original 10nm was canned just after printing 1 SKU.

 

[Doug S]

It didn't.
Apple launched N3B products well before Intel did.
And ARL launched in lock step with MTL, it was the knockback effect of MTL delays that pushed everything back for Intel, not TSMC N3B delays.

When Apple launched N3B products versus when Intel did doesn't necessarily tell us anything about whether Intel could have launched their N3B stuff earlier. Apple prepaid for a ton of N3B wafers - they needed M3 to ship millions of iPad Pros then A15P to ship many many millions of iPhones, then additional M3 plus M3P/M3M for millions of Macs, all in a matter of months. We don't know if Intel's timing launching after all that was because they weren't ready to launch earlier, or if Apple was soaking up 100% of capacity and Intel had to wait for wafer starts to become available for them.

 

[Joe NYC]

In server environment, not having SMT would be a serious handicap vs. AMD.

Could be. We will see how it pans out.

It seems like LBT is also recognizing this (removal of SMT) as a big mistake on part of Intel that he intends to fix.
(my interpretation of his comments)

 

[Geddagod]

It seems like LBT is also recognizing this (removal of SMT) as a big mistake on part of Intel that he intends to fix.
(my interpretation of his comments)

You are prob right

When Apple launched N3B products versus when Intel did doesn't necessarily tell us anything about whether Intel could have launched their N3B stuff earlier. Apple prepaid for a ton of N3B wafers - they needed M3 to ship millions of iPad Pros then A15P to ship many many millions of iPhones, then additional M3 plus M3P/M3M for millions of Macs, all in a matter of months. We don't know if Intel's timing launching after all that was because they weren't ready to launch earlier, or if Apple was soaking up 100% of capacity and Intel had to wait for wafer starts to become available for them.

Intel was also rumored to have done a large pre-payment and launch close to Apple.

 

[DrMrLordX]

Intel was also rumored to have done a large pre-payment and launch close to Apple.

Pretty sure they did. TSMC converted an entire research fab to production for Intel's N3B order.

 

[Quintessa]

Apple prepaid for a ton of N3B wafers...

Intel may have had N3B designs ready but couldn't fab them until Apple loosened their chokehold on TSMC capacity. Also, don't forget:

• Apple tends to lock N3B for mobile. Intel's likely chasing high-performance laptop/Desktop SKUs, which are more yield/power-sensitive.
• Intel's unified core architecture (Panther Lake and beyond) reportedly leans into SMT-only P-cores againa signal that they're acknowledging some of the fragmentation inefficiencies of E/P-core split.
• The leap from 7/Intel 4 to N3B/N2 is massive in toolchain and IP porting. Apple has years of N5/N3 experience, Intel doesn't.

So yeah, could they have launched earlier? Maybe. But there's a real possibility Apple's fab priority delayed Intel, not just Intel's own readiness.

 

[511]

Intel may have had N3B designs ready but couldn't fab them until Apple loosened their chokehold on TSMC capacity. Also, don't forget:

• Apple tends to lock N3B for mobile. Intel's likely chasing high-performance laptop/Desktop SKUs, which are more yield/power-sensitive.
• Intel's unified core architecture (Panther Lake and beyond) reportedly leans into SMT-only P-cores againa signal that they're acknowledging some of the fragmentation inefficiencies of E/P-core split.
• The leap from 7/Intel 4 to N3B/N2 is massive in toolchain and IP porting. Apple has years of N5/N3 experience, Intel doesn't.

So yeah, could they have launched earlier? Maybe. But there's a real possibility Apple's fab priority delayed Intel, not just Intel's own readiness.

P/E are getting replaced by Unified Core based on atom but LBT wants that they keep HT with going unified also N3B didn't clock much high lol