But if the SOC die is different like it is rn, they lose a bunch of battery life, so Intel would have to figure something out for that.
But my main point there was that the 8+16 N2 die looks like it is going to get
a lot of use lol.
Where they can simply swallow the cost
Exactly, but other segments can't swallow the cost. The reason Intel is using 18A-P there is purely a financial reason, not because of Intel 18A-P being close to N2.
Who is going to sponsor them they don't have too much money left if they want to ramp quickly they need money they are just giving them the maximum flexibility in terms of operation and cost ramping a fab cost $$$ they don't have much money.
If this is the case, the IO die, iGPU die, and Wildcat Lake can all be shifted over to different nodes or have their plans changed to accommodate 8+16 dies on 18A-P.
Intel is wasting a bunch of money, and is also getting a bunch of bad investor press, by going external. So they have the money to do large payments to TSMC to use their N2 node, but not enough to expand capacity for 18A? You aren't even building whole new fabs, all you are doing is expanding capacity.
Capacity reason makes 0 sense. Even Intel isn't claiming this is the case- it's performance and timing apparently.
And the timing reason is BS too...
Wild cat is like 70mm2 at max lol with 2+4 config.
It's low end, high volume product.
Also a 8+16 tile isn't all that much larger than that estimate (no idea how accurate it is).