Incoming ! ** Update ** Its alive !!! And comparison to Rome 64 core !

[Markfw]

I have 2 7763 QS sample CPUs. But the motherboard is delayed in China for some reason (yes, it could be the new rules)

256 threads incoming !

 

[Shmee]

:/ hopefully it comes soon! What motherboard?

 

[Markfw]

:/ hopefully it comes soon! What motherboard?

Supermicro
MBD-H12DSi-N6-O

 

[Markfw]

Its here!! 128 gig more to install got 384 gig total ! 2TB PCIE gen 4 NVME.

 

[Markfw]

What I had forgotten, was that supermicro does NOT use standard locations for the standoff's, so a lot of work has to go into getting it in the case, with zip ties as well....

 

[Markfw]

OK, I can press del when I see the supermicro screen and see bios options. I though I had boot options set correctly, but when I boot I get 2 or 3 variants of this screen:



Then I get this screen, but I have no idea how to install windows or linux. WTF is going on ? I did not have this problem with the supermicro motherboard before

 

[Skillz]

It looks like you are using the PXE boot option.

 

[Markfw]

Not trying to let it do that, but...

First, it does NOT like anything but the built in video port. Second, win 10 locks up. 3rd, its installing mint 20.3 !!!

 

[Markfw]

Its alive !!

 

[Markfw]

I would do BOINC, so I could see in the morning, but I don't want to blow fuses. Tomorrow I load it.

 

[cellarnoise]

I would do BOINC, so I could see in the morning, but I don't want to blow fuses. Tomorrow I load it.

I'd like to say, "that's what she said", but it is probably inappropriate...

 

[StefanR5R]

What I had forgotten, was that supermicro does NOT use standard locations for the standoff's, so a lot of work has to go into getting it in the case, with zip ties as well....

While the product page says "EATX" (which isn't any standard at all), it's actually SSI-EEB. Here is an archived version of the SSI-EEB spec: -> PDF (v1.0.1 of 2011)
There are several options for motherboard standoff locations, but Supermicro still deviates a little (at least from this particular version; I don't know of other versions of the spec). Supermicro's layout conforms with the specified grid lines, but they chose other intersections of the grid lines for one or another standoff.

 

[pututu]

@Markfw, what's the all-core frequency for the QS chip?

 

[Markfw]

@Markfw, what's the all-core frequency for the QS chip?

Its supposed to be 2.45, but so far its only up to 2281. loaded with Rosetta tasks.
Mark@mark-dual-7763:/var/lib/boinc$ lscpu
Architecture: x86_64
CPU op-mode(s): 32-bit, 64-bit
Byte Order: Little Endian
Address sizes: 48 bits physical, 48 bits virtual
CPU(s): 256
On-line CPU(s) list: 0-255
Thread(s) per core: 2
Core(s) per socket: 64
Socket(s): 2
NUMA node(s): 2
Vendor ID: AuthenticAMD
CPU family: 25
Model: 1
Model name: AMD Eng Sample: 100-000000314-04_30/16_N
Stepping: 0
Frequency boost: enabled
CPU MHz: 2281.898
CPU max MHz: 1600.0000
CPU min MHz: 1200.0000
BogoMIPS: 3200.10
Virtualization: AMD-V
L1d cache: 4 MiB
L1i cache: 4 MiB
L2 cache: 64 MiB
L3 cache: 512 MiB
NUMA node0 CPU(s): 0-63,128-191
NUMA node1 CPU(s): 64-127,192-255
Vulnerability Itlb multihit: Not affected
Vulnerability L1tf: Not affected
Vulnerability Mds: Not affected
Vulnerability Meltdown: Not affected
Vulnerability Mmio stale data: Not affected
Vulnerability Spec store bypass: Mitigation; Speculative Store Bypass disabled via prctl and seccomp
Vulnerability Spectre v1: Mitigation; usercopy/swapgs barriers and __user pointer sanitization
Vulnerability Spectre v2: Mitigation; Retpolines, IBPB conditional, IBRS_FW, STIBP always-on, RSB filling,
PBRSB-eIBRS Not affected
Vulnerability Srbds: Not affected
Vulnerability Tsx async abort: Not affected
Flags: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush
mmx fxsr sse sse2 ht syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc r
ep_good nopl nonstop_tsc cpuid extd_apicid aperfmperf pni pclmulqdq monitor ssse
3 fma cx16 pcid sse4_1 sse4_2 x2apic movbe popcnt aes xsave avx f16c rdrand lahf
_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw i
bs skinit wdt tce topoext perfctr_core perfctr_nb bpext perfctr_llc mwaitx cpb c
at_l3 cdp_l3 invpcid_single hw_pstate ssbd mba ibrs ibpb stibp vmmcall fsgsbase
bmi1 avx2 smep bmi2 erms invpcid cqm rdt_a rdseed adx smap clflushopt clwb sha_n
i xsaveopt xsavec xgetbv1 xsaves cqm_llc cqm_occup_llc cqm_mbm_total cqm_mbm_loc
al clzero irperf xsaveerptr wbnoinvd arat npt lbrv svm_lock nrip_save tsc_scale
vmcb_clean flushbyasid decodeassists pausefilter pfthreshold v_vmsave_vmload vgi
f umip pku ospke vaes vpclmulqdq rdpid overflow_recov succor smca
mark@mark-dual-7763:/var/lib/boinc$

 

[Markfw]

So, its fully loaded, no blown breakers yet. And runs WAY cooler than the dual 7601's.

 

[Markfw]

Best estimate at this point. 3.5 hours for the 7B12 (the fastest 64 core Rome I have) for a Rosetta task. 2.5 hours for the 7763 Milan !

Edit: later in the estimate, now its 2:55 for the dual 7763, and the 7B12 is 2:55.Same... CRAP, I thought it would be faster.

 

[pututu]

2.281 GHz number is lower than I expected. Can you try to run this command and see how each core is doing: watch -n1 "cat /proc/cpuinfo | grep \"^[c]pu MHz\"" ? Maybe this is just a QS version which usually has 100 to 200MHz lower clock than retail.

Also, I usually set the "cTDP Control" in the BIOS to the max of the cpu. For 7763, it should be able to configure from 225W to 280W in "Manual" mode. Just to be sure.
While if you are at it, might worth trying to change the "Determinism Slider" to "Power" and see if the core clock does boost a bit higher.

BTW, I thought Rosetta task is based on run time that you set in your account preference.

 

[Markfw]

2.281 GHz number is lower than I expected. Can you try to run this command and see how each core is doing: watch -n1 "cat /proc/cpuinfo | grep \"^[c]pu MHz\"" ? Maybe this is just a QS version which usually has 100 to 200MHz lower clock than retail.

Also, I usually set the "cTDP Control" in the BIOS to the max of the cpu. For 7763, it should be able to configure from 225W to 280W in "Manual" mode. Just to be sure.
While if you are at it, might worth trying to change the "Determinism Slider" to "Power" and see if the core clock does boost a bit higher.

BTW, I thought Rosetta task is based on run time that you set in your account preference.

View attachment 69385

actually I prefer the 225 watt setup, as I already have a lot of heat, and those heatsinks may only be good for 250.

The output is a little over 2200 to a little over 2300.

 

[mmonnin03]

Rosetta is not a project to use when comparing CPU performance as tasks will run to the set time given. The CPU time, not run time. All my Rosetta tasks run for 12 hours from the 1950x to 5950x. Credit is different but run times are the ~ same.
Something with a consistent WU runtime (not Universe) would be a better comparison for CPU performance. WCG, NFS, Cosmology, SiDock, TN-Grid.

 

[Markfw]

Here is a good one. Under Rosetta and 256 tasks, I get coil whine and 2300 mhz. Under TN-Grid and 256 tasks, I get 2562 and NO coil whine. Obviously the Rosetta tasks are more stressful. I must be hitting some max.

 

[StefanR5R]

At same core count, Milan with its somewhat wider cores is faster than Rome

• in workloads which are not power constrained,
• in special cases which benefit from the different CCX layout (up to 8c/16t and 32MB L3$ per CCX in Milan, up to 4c/8t and 16MB L3$ per CCX in Rome).

Vice versa, in workloads which are power constrained = many all-core loads, the performance difference between Milan and Rome is expected to be rather small.

I usually set the "cTDP Control" in the BIOS to the max of the cpu. For 7763, it should be able to configure from 225W to 280W in "Manual" mode.

I wonder what the cTDP_high of 7B12 is. Maybe 240 W like some other 64-core Rome SKUs, or maybe 280 W like 7H12?

Also remember that both TDP and PPT are recommended to be set to the same value, in case of Rome, and probably Milan too.

 

[Markfw]

At same core count, Milan with its somewhat wider cores is faster than Rome

• in workloads which are not power constrained,
• in special cases which benefit from the different CCX layout (up to 8c/16t and 32MB L3$ per CCX in Milan, up to 4c/8t and 16MB L3$ per CCX in Rome).

Vice versa, in workloads which are power constrained = many all-core loads, the performance difference between Milan and Rome is expected to be rather small.


I wonder what the cTDP_high of 7B12 is. Maybe 240 W like some other 64-core Rome SKUs, or maybe 280 W like 7H12?

Also remember that both TDP and PPT are recommended to be set to the same value, in case of Rome, and probably Milan too.

Well, all my EPYC motherboards are set to defaults, no PPT or TDP changes. So I have one 7B12, and 2 Milan 7763's, and now (coming) 2 7V12's. And 2 7742's. Just those are 896 threads !

 

[TennesseeTony]

256 threads didn't quite sink into my brain, until I saw the screenshot that you had to scroll down to see all the processors.