IDE / PCI bus throughput question...

busmaster11

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Mar 4, 2000
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Can someone post specs or links to where I can find this stuff? I want to know the following:

what is max throughput of the PCI bus?

What is the max throughput of ata/133 and all the IDE standards prior to it, Ata/33, udma, dma, pio1-4, etc..?

On-chipset IDE controllers and on-motherboard RAID controllers all squeeze through the same PCI bus, correct?

Thanks...

 

Wolfsraider

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Jan 27, 2002
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actually i couldn't find anything there so from memory


<< what is max throughput of the PCI bus >>


on a 32 bit bus 133 mb
on a 64 bit bus 533 mb


<< What is the max throughput of ata/133 and all the IDE standards prior to it, Ata/33, udma, dma, pio1-4, etc..? >>


ata 133=133mb ata 100=100mb ata 66=66mb ata 33=33mb (theoretical the numbers are usually much lower

udma? dma? pio? can't help you;)sorry




<< On-chipset IDE controllers and on-motherboard RAID controllers all squeeze through the same PCI bus, correct? >>


again don't know sorry
 

busmaster11

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Mar 4, 2000
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<< actually i couldn't find anything there so from memory


<< what is max throughput of the PCI bus >>


on a 32 bit bus 133 mb
on a 64 bit bus 533 mb
>>


Are you sure about that second one? I thought storage review puts it much lower than that, but I could be wrong. So you saying that ata/133 when maxed out completely maxes out the pci bus?
 

Wolfsraider

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i asked a similar question about raid 0 on two scsi 36lp drives and thats the figures by andy on maxing out the pci bus on a 32 bit bus

i'll see if i can find it for you
 

Wolfsraider

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Jan 27, 2002
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<< Are you sure about that second one? I thought storage review puts it much lower than that, but I could be wrong. So you saying that ata/133 when maxed out completely maxes out the pci bus? >>



if your talking about the 64bit bus remember there are 64 bit 66 mhz=533 and 64 bit 33 mhz bus=266
 

AndyHui

Administrator Emeritus<br>Elite Member<br>AT FAQ M
Oct 9, 1999
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In all current chipset implementations from Intel, SiS and VIA (ALi and AMD are exceptions), the onboard chipset South Bridge IDE Controllers do not share PCI bandwidth with "onboard" Controllers such as a Promise ATA Controller mounted onto the motherboard.

Although the onboard IDE is a PCI device, it does not share the same bus.

ATA133 can potentially max out the PCI bus, say a PCI Card controller (which does have to share PCI bandwidth with the other PCI cards running in the system, but unless you are running in a RAID Configuration, maximum burst rates, STR and overheads are not going to get to 133MB/s.

Link to conversation with wolfsraider
 

Rand

Lifer
Oct 11, 1999
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PIO Mode 0: 3.3MB/s
PIO Mode 1: 5.2MB/s
PIO Mode 2: 8.3MB/s
PIO Mode 3: 11.1MB/s
PIO Mode 4: 16.7MB/s

There is also PIO Mode 5, but that is not an official standard, and peaks at 22.2MB/s.

Single word DMA mode 0: 2.1MB/s
Single word DMA mode 1: 4.2MB/s
Single word DMA mode 2: 8.3MB/s

Multiword Mode 0: 4.2MB/s
Multiword Mode 1: 13.3MB/s
Multiword Mode 2: 16.7MB/s

Multiword UDMA Mode 0: 16.7MB/s
Multiword UDMA Mode 1: 25.0MB/s
Multiword UDMA Mode 2: 33.3MB/s
Multiword UDMA Mode 3: 44.4MB/s
Multiword UDMA Mode 4: 66.7MB/s
Multiword UDMA Mode 5: 100.0MB/s
Multiword UDMA Mode 6: 133.3MB/s


32bit/33MHz PCI: 127.2MB/s
64Bit/33MHz PCI: 254.1MB/s
64bit/66MHz PCI: 508.6MB/s

UDMA33, UDMA 66 etc are all marketing names, and not official standards.
The term UDMA 33 correlates to UDMA Mode 2, UDMA66= UDMA Mode 4 etc etc.
 

busmaster11

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Mar 4, 2000
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<< In all current chipset implementations from Intel, SiS and VIA (ALi and AMD are exceptions), the onboard chipset South Bridge IDE Controllers do not share PCI bandwidth with "onboard" Controllers such as a Promise ATA Controller mounted onto the motherboard.

Although the onboard IDE is a PCI device, it does not share the same bus.

ATA133 can potentially max out the PCI bus, say a PCI Card controller (which does have to share PCI bandwidth with the other PCI cards running in the system, but unless you are running in a RAID Configuration, maximum burst rates, STR and overheads are not going to get to 133MB/s.

Link to conversation with wolfsraider
>>


Very very interesting - AndyHui - so are there two separate PCI buses? I was wondering why an in-chipset IDE controller would want to leave to join the public PCI bus - it would not seem very efficient... So what classifies the Southbridge IDE controller a PCI device?

Well, you just answered my big question... As a reward, I'll make another request... You got links to this info? :)
 

AndyHui

Administrator Emeritus<br>Elite Member<br>AT FAQ M
Oct 9, 1999
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There are multiple separate busses that are controlled by the chipset South Bridge. One for PCI, one for IDE, one for USB, and others for onchip sound or LAN.

I'm at work at the moment, so I'll provide you with chipset architecture diagrams later.