IDE Latency to high?

[Silan]

Sandra2002 is reporting my IDE controller latency is to high. It tells me its running at 128 clocks. Should i believe Sandra and if so is this hindering my performance?


P4 1.6
Jetway S446(SIS 645 Chip)

 

[Peter]

See, that's why techy tools are for techy people PCI Latency Timer is the amount of time that a
given bus master device may keep ownership of the PCI bus for a transmission, before releasing it
so a new arbitration allows another PCI device to win ownership.

Larger values increase throughput of _this_ PCI device (at the expense of all others), smaller values
increase overall fairness.

So if you want IDE performance to be good, and don't have much more high bandwidth PCI gear,
leave it like it is.

And on the SiS chipsets, this doesn't matter at all, since the IDE channels have their own high speed
connection to the chipset core - they aren't even on the PCI bus.

regards, Peter