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News IBM open sources A2O CPU core

NTMBK

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A2O open sourced for enhanced single-thread performance
The A2O core is an out-of-order, multi-threaded, 64-bit POWER ISA core that was developed as a processor for customization and embedded use in system-on-chip (SoC) devices. It’s most suitable for single thread performance optimization. A follow-up to its parent high-streaming throughput A2I predecessor, it maintains the same modular design approach and fabric structure. The Auxiliary Execution Unit (AXU) is tightly-coupled to the core, enabling many possibilities for special-purpose designs for new markets tackling the challenges of modern workloads.
Speaking of the A2O at OpenPOWER Summit 2020, Mendy Furmanek, President of the OpenPOWER Foundation and Director of POWER Open Hardware Business Development at IBM, said, “I’m excited to announce the opening of the out-of-order A2O core design. A2O provides enhanced single-thread performance and is a perfect companion to the highly scalable 4-way SMT commercialized A2I core. These, combined with the ease of entry Microwatt core, do an excellent job of showcasing the versatility of the Power ISA.”





Interesting timing, with the news about ARM and NVidia. Looks like they're trying to get back some of the embedded market from ARM- and they have a lot of established tooling and software, which gives them a leg up over RISC-V.
 

DrMrLordX

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POWER has been open for awhile anyway, hasn't it? Is this core new, or is it something that IBM simply hadn't open-sourced through OpenPOWER previously?
 

SarahKerrigan

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New cores derived from A2 which is from 2010.
Not really "derived from" since A2I is VHDL and A2O is Verilog, and they're pretty radically different at the uarch level.

POWER has been open for awhile anyway, hasn't it? Is this core new, or is it something that IBM simply hadn't open-sourced through OpenPOWER previously?
It's an old core (early 2010s), newly open-sourced.
 

NostaSeronx

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Sep 18, 2011
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Not really "derived from" since A2I is VHDL and A2O is Verilog, and they're pretty radically different at the uarch level.
A2 OoO is completely derived from A2 InO, which is derivied from the A2 processor in POWER-EN/POWER-A2. VHDL vs Verilog doesn't matter on the blueprint, that the architecture A2O and A2I are from A2. It wouldn't be called A2O if it wasn't derivative. ∞% derived from A2 and A2I.

They aren't true OpenPOWER till they switch to ISA 3.x, anyway:
-> The A2I core is compliant to Power ISA 2.06 and will need updates to be compliant with either version 3.0c or 3.1. Power ISA 3.0c and 3.1 are the two Power ISA versions contributed to OpenPOWER Foundation by IBM.
-> The A2O core is compliant to Power ISA 2.07 and will need updates to be compliant with either version 3.0c or 3.1. Power ISA 3.0c and 3.1 are the two Power ISA versions contributed to OpenPOWER Foundation by IBM.

Do to the open-source nature => A2I on Verilog, A2O on VHDL; is completely an option for maximum coverage. Both are needed for real ASICs anyway for Verilog and VHDL co-simulation.
 
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NTMBK

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It's an old core (early 2010s), newly open-sourced.
Yeah, as the comments on the Github page mention, this is originally a 45nm CPU. So I imagine it's pretty far behind the latest state of the art in low-power CPUs. I wonder how it stacks up performance-wise to a Cortex A55?
 

SarahKerrigan

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Yeah, as the comments on the Github page mention, this is originally a 45nm CPU. So I imagine it's pretty far behind the latest state of the art in low-power CPUs. I wonder how it stacks up performance-wise to a Cortex A55?
Being out of order and multithreaded, I'd guess it probably beats an A55 at iso clock, especially at MT loads - but it's hard to say. Maybe at some point I'll simulate it and run some SPEC traces.
 

Thala

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Nov 12, 2014
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Okay. I did notice it being 45nm (as @NTMBK noted) which sort of threw me for a loop. Might be more-interesting if someone took the design, put it through an optical shrink, and sold it for cheap.
What are you talking about? It is IP at RTL level - there is no process node associated to it.
 

Thala

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@DrMrLordX

You are still making no sense. RTL is still process node agnostic - even if someone made a 45nm implementation out of it in the past.
What would be the process, which you are trying to describe with "put it through an optical shrink"...? There is no shrink involved - as the fact that someone did a 45nm implementation in the past has no relevance.
 
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DrMrLordX

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@DrMrLordX

You are still making no sense. RTL is still process node agnostic - even if someone made a 45nm implementation out of it in the past.
Alright, I'll accept that. Honestly I didn't know. Typically, when a CPU has already been designed and masked for a particular node, doing a node shrink requires more work.
 

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