IBM may drop low-k materials for advanced ICs

[Mr.IncrediblyBored]

http://www.eetimes.com/semi/news/OEG20030417S0042

IBM may drop low-k materials for advanced ICs

By David Lammers
EE Times
April 17, 2003 (3:33 p.m. ET)

AUSTIN, Texas ? IBM Microelectronics is considering abandoning the SiLK low-k spin-on dielectric material for advanced semiconductors, according to sources inside and outside the company. IBM has yet to ship a volume product created with SiLK, the sources said.
?There is an internal battle going on [at IBM] whether to continue to try to work through the thermal-expansion problems with SiLK, or give up on it and use a CVD [chemical vapor deposition] material,? said one knowledgeable source at the International Reliability Physics Symposium in Dallas earlier this month.

Though SiLK is said to be more easily extended to lower k-values, its coefficient of thermal expansion (CTE) is much higher than CVD carbon-doped oxides, causing the dielectric to separate from copper interconnects in a chip, the sources said. The delamination issue has been most troublesome at the point where interconnect vias attach to copper wires.

Interesting. If IBM decides to drop the SiLK project, it certainly kills any process advantage IBM had over TSMC for nVidia at 130nm. Seems likely at this point that nV35 will remain at 130nm with traditional high-k dieletric (flourinated silicate glass - FSG).

I had another thread in Highly Technical (apparently didn't catch anybody's interest) that is related to this. I guess IBM would be one of the struggling fabs?

Some fabs struggle with low-k interconnect materials, while remaining industry preps for high-k gate insulators..

 

[pm]

If IBM decides to drop the SiLK project, it certainly kills any process advantage IBM had over TSMC for nVidia at 130nm.

Any process advantage? In interconnect anyway.

 

[Mr.IncrediblyBored]

Originally posted by: pm

If IBM decides to drop the SiLK project, it certainly kills any process advantage IBM had over TSMC for nVidia at 130nm.

Any process advantage? In interconnect anyway.

True. That was primarily what I was aiming at.😱