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http://www.siliconstrategies.com/story/OEG20021204S0041
IBM discloses combo strained-silicon/SOI technology
By Mark LaPedus
Semiconductor Business News
(12/04/02 07:30 p.m. EST)
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EAST FISHKILL, N.Y.--IBM Corp.'s Microelectronics Division next week is expected to announce a radical and combination strained-silicon/silicon-on-insulator (SOI) technology for use in making high-performance chips at the 65-nm (0.065-micron) node.
IBM has already fabricated an SRAM, based on the ?strained-silicon-on-SOI? technology in the lab, but commercial chip products are not due out until the 65-nm node in the 2005 time frame, according to officials from the East Fishkill-based organization.
hehe i like this part
The company still claims it is still ahead of Intel in the process technology race. ?Intel is developing strained-silicon on bulk at 90-nm,? Lee said. ?We don't see the need to have strained-silicon at 90-nm, because SOI intrinsically has better performance [than strained-silicon at 90-nm],? he said.
IBM discloses combo strained-silicon/SOI technology
By Mark LaPedus
Semiconductor Business News
(12/04/02 07:30 p.m. EST)
Archives
EAST FISHKILL, N.Y.--IBM Corp.'s Microelectronics Division next week is expected to announce a radical and combination strained-silicon/silicon-on-insulator (SOI) technology for use in making high-performance chips at the 65-nm (0.065-micron) node.
IBM has already fabricated an SRAM, based on the ?strained-silicon-on-SOI? technology in the lab, but commercial chip products are not due out until the 65-nm node in the 2005 time frame, according to officials from the East Fishkill-based organization.
hehe i like this part
The company still claims it is still ahead of Intel in the process technology race. ?Intel is developing strained-silicon on bulk at 90-nm,? Lee said. ?We don't see the need to have strained-silicon at 90-nm, because SOI intrinsically has better performance [than strained-silicon at 90-nm],? he said.