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Discussion i7-5775C: the blast from the past - Effect of large L4 cache in high-refresh-rate gaming

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Gideon

Golden Member
Nov 27, 2007
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Ian is in the middle of updating the Anandtech bench results for 2020 CPU tests.

He recently added the Broadwell i7-5775C desktop CPU, the one with 128 MB EDRAM L4 on a separate die. With all the Zen 3 L3 hype going on, I took a peak how is this CPU performing now, in games as High-Refresh rate gaming really wasn't a thing back then and the GPUs were the absolute bottleneck.

I was really surprised by the results.

Not only does the i7-5775C (3.3 base, 3.7 boost) win handily vs the i7-4790K (4.0 base 4.4 boost) Haswell:

In a number of charts it beats every single current CPU, despite being a lowly-clocked 4/8 Broadwell core:

Civilization VI - 1080p Max (1st in both FPS and 95th Percentile)
Strange Brigade 1080p Ultra (1st in both FPS and 95th Percentile)
F1 2019 1080p Ultra (4th beating everything south of 10600K in both FPS and 95th Percentile)

Now obviously it's a small subsample of the games and it doesn't fair anywhere near as well in others like FF 15, Borderlands 3 (and probably any heavily multithreaded games like BF5).

But still, comparing it to even the 7700K (that has a slight IPC advantage and nearly a GHz clock-speed advantage) it's still nect-to-neck. I'd even say that in gaminig benchmarks the 7700K loses more than it wins (in productivitiy it's obviously the other way around).

Really impressive overall! Too bad those Crystal Well EDRAM caches never manifested themselves in later CPUs. Can't imagine how well a modern chip with 14nm 256MB off-die EDRAM would perform now.
 

LightningZ71

Senior member
Mar 10, 2017
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Given that the 12 and 16 core chips can have 64MB of L3 combined, the L4 would need to be at least twice that amount to be effective as a strictly victim cache and 4x as much if it was also going to be doing pre-fetch buffering too. The IO die is already rather large as it is. Even with their improved 12nm procss, cramming 128-256 MB into it won't work from a die size point of view. I don't think that GloFo has the needed die stacking techniques to even stack it on the IO die.
 

moinmoin

Platinum Member
Jun 1, 2017
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Given that the 12 and 16 core chips can have 64MB of L3 combined, the L4 would need to be at least twice that amount to be effective as a strictly victim cache and 4x as much if it was also going to be doing pre-fetch buffering too. The IO die is already rather large as it is. Even with their improved 12nm procss, cramming 128-256 MB into it won't work from a die size point of view. I don't think that GloFo has the needed die stacking techniques to even stack it on the IO die.
Such a massive L4$ shouldn't be on the same die using the same node anyway considering IO logic scales poorly while cache scales really well. This would be a candidate for X3D stacking or whatever, using the best fitting nodes per layer.
 

IntelUser2000

Elite Member
Oct 14, 2003
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Even Intel realized these problems and in Skylake gen moved from L4 cache with tags to "system side" L4 memory cache, but i don't think they had much success with those either.
Skylake had some success with the Iris Plus(not to be confused with the Iris Pro, which are -H parts and using 45W or more) parts and upselling them as the premium+ config in already very expensive clamshells and 2-in-1s.

They probably gave it up because Gen 11 GPU on Icelake was able to beat it while abandoning the eDRAM. Tigerlake ups the performance further and still no eDRAM.

It's way better performance/cost wise to put a single HBM2 stack in there anyway.
 
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IntelUser2000

Elite Member
Oct 14, 2003
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It eats into thermals fairly heavily. It's also no friend to total package power budgets.
Thermals/power shouldn't be a problem. Its rated at 3W with the first generation eDRAM in the Haswell Iris Pro having 1W standby. The second generation(I forgot where it was first used, but Skylake definitely uses it) cuts that to a quarter or something so you no longer have to sacrifice battery life going for eDRAM.
 

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