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I have a theory

Rich85

Member
My theory is that if you have say 2x512mb of OCZ 3200 VOLTAGE EXTREME and under clocked them to say pc2700 or pc2100 speeds, could you then up the volts and then lower the timings to have super tight timings of 1-1-1-x or close...

Like i said this is just a theory of mine (it is probably technicaly totaly incorrect, if any one would share there thoughts that would be great..

please inlighten me if this in theory could be done ... and if so what would the performance be like???
 
the memory is probably able to do that, its the memory controller i have doubts about. it was never intended to run like that. to some degree, memory can usually give or take latency as you move the frequency in one direction.

not really new info here, just not worth the effort since most all memory controllers can't even do those settings.
 
OCZ VE mem's are just upgraded performance memory, the platnum EB and GOLD series still produce better latencies.
 
actually lower latenciesis better isnt it? werent the early ddr2 modules slower than pc3200 memory because of higher latencies?
 
I thought DDR couldn't go below 2-2-2-2 timings because of the way it operates, you would need sdr ram to go down to 1-1-1-1 timings.(since it only transfers information once per clock)
 
Ever since OCZ and PDP released their ultra low latency DDR2 rams that can achieve speeds of up to +700mhz, there is no longer this significant gap between DDR and DDR2.

I would imagine cas1 to be impossible.
 
yes, latency is important, but i don't know if it's important enough to run DDR266 just to get better latency. Bandwidth higher than DDR400 might not make a huge performance boost, but I imagine that there would be a huge performance hit to running a 2+ GHz processor with DDR266 or lower memory. That's just not enough bandwidth.
 
Originally posted by: HannibalTheCannibal
Originally posted by: Fox5
I thought DDR couldn't go below 2-2-2-2 timings because of the way it operates, you would need sdr ram to go down to 1-1-1-1 timings.(since it only transfers information once per clock)

My thoughts exactly.

I was going to say the same thing, but I think that those timings are not measured in clock cycles, but nanoseconds.
 
First find a board that can tune the timings down that low. Additionally adjusting the IIRC TRAS (Whichever one is normally at 7 or 9 or 11) wont do anything by going lower.

Command Rate is already at 1T unless you are running with all banks full. 1T means that data is transmitted on the rise and the fall of the clock, whereas 2T it is only transmitted on the rise i believe.

This would be kind of pointless because JEDEC standard is PC3200, with any processor you are crippling its memory bandwidth. But nonetheless an interestsing experiment.

-Kevin
 
Originally posted by: mwmorph
actually lower latenciesis better isnt it? werent the early ddr2 modules slower than pc3200 memory because of higher latencies?

"early"?
DDR2 runs at half the speed of DDR internally. That's why the bus speed can be increased and also why some of the signal problems of DDR goes away. (though there are other improvements too). It's also why latencies are always going to be higher with DDR2. Don't worry, with higher speeds and more ram, we'll soon forget about this little beloved patriot.
 
Originally posted by: Fox5
I thought DDR couldn't go below 2-2-2-2 timings because of the way it operates, you would need sdr ram to go down to 1-1-1-1 timings.(since it only transfers information once per clock)

hmm, im running 1.5 on the cas latency though
 
I was going to say the same thing, but I think that those timings are not measured in clock cycles, but nanoseconds.

Hmm, I'm not so sure. The thing is, I don't think current ddr memory is capable of sub 10ns response times, secondly the latencies do go down if the timings stay the same but clock speed is raised.
 
Originally posted by: stardust
OCZ VE mem's are just upgraded performance memory, the platnum EB and GOLD series still produce better latencies.

Sorry but the VX memory will produce the best timmings than any memory (exept bh-5) as long as its under 265 fsb.
 
Those timings are expressed in clock cycles, but obviously they have to correlate to actual time intervals in seconds (or nanoseconds, as the case may be). DDR400 memory at CL2.5 means the latency 2.5 x .0025 microseconds, or 2.5*2.5nanoseconds, or 6.25 nanoseconds. You could run the same memory at DDR266 speed, CL2 which would be .0037 microseconds * 2 or 7.4 nanoseconds. You might be able to run it at DDR333 CL2 though that would be pushing it, 6.0nanoseconds. DDR500 memory at CL3 is 6.0 nanosecond memory, which will run safely at DDR333, CL2.
 
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