... to find out how this little ISA IDE controller works. 
It was on my desk, so I picked it up.
I had it in my hand, so I looked at it.
I was looking at it, and I wondered just how it worked with only a few simple ICs.
I'm setting to work.
The wiring of this thing is so simple I think I'll just run down the ISA slot and trace each set of pins in general.
On second thought, I'll group 'em logically to some extent. Ah, who cares, you aren't actually going to read this, are you?
The 8 data lines (A2-A9) of the 8bit bus run directly to a SN74LS245N, which is a simple transceiver, and that IC is wired to some of the data lines on the IDE port.
The 8 additional data lines (C11-C18) of the 16 bit extension run directly to another SN74LS245N, which is wired to the remaining data lines on the IDE port. Interesting thing here is, it looks like one 245N handles the odd IDE pins, and the other handles the even. This makes the PCB simpler, plus because of the way IDE ports are laid out, one chip ends up handling IDE data lines 0-7, while the other gets 8-15. So, in summary of these two points, the 16 I/O data lines of the extended ISA bus are essentially connected directly to the 16 data lines on the IDE cable, straight up, bit 0 to bit 0, bit 1 to bit 1, etc.
Moving on....
(A10) leads to a blank drillhole, it goes nowhere on this particular board revision.
(A11) is "address enable" on the ISA bus, and evidently goes high when DMA is in control. It runs to the "output enable" of the most interesting chip on the board, an AMD PALCE20V8H. This thing is some kind of programmable logic, so I shouldn't really try to guess what it does yet.
Ack, things just got weird.
(A22-A30) are address bits (strictly output from the motherboard) on the ISA, and they run directly into appropriate input lines on that interesting AMD chip I just mentioned. Notice that those are only bits 1-9. Bit 0 is strange.
(A31), ISA address bit 0, runs to a SN74LS244N, which is little more than a buffer. (A31)'s signal eventually finds itself at IDE pin 35, which in IDE-eese, is address bit 0. OK, so, while weird, it makes some sense.
Where did it's 9 brethren go? I'll just follow the outputs from the AMD chip and assume that's directly related to them.
Lines from the PALCE20V8H run to:
- IDE pin 1, the IDE reset line
- IDE pin 38, which has something to do with IO address 3F6-3F7, so this has something to do with setting the address at which to find the IDE interface I assume. Strange (to me at least) that that information is actually on the cable.
- one of the 245N's output enable line
- IDE pin 37, another IO address select line, this time 1F0-1F7
- through a capacitor to ground
- to the output enable line of the other 245N
- through a resistor to Vcc
- deadend (absent part)
OK, so that wraps up the goofy, unpredictable chip. Moving on to the B and D ISA pins...
(B1) is ground
(B2) is the system reset trigger, and it runs to capacitor->ground pin on the AMD chip. So the cap may be providing a simple automatic power-on reset command.
(B3) is +5v
(B10) is another ground
(B13) sets I/O write mode on the ISA, and runs through the 244N to IDE pin 23, which is the IDE write mode line
(B14) sets I/O read mode on the ISA, and runs through the 244N to IDE pin 25, which is similarly the IDE read mode line
(B29) is another +5v
(B31) is another ground
(D2) reports a 16bit I/O chip to the motherboard, but I can't figure out where the line goes on this board
(D3-D7) are IRQ request lines for interrupts 10-14, respectively, and with the exceptions of (D5) IRQ 12 and (D7) IRQ 14, they all run to a SN74LS125AN, another buffer. The buffer chip is then connected to the strange AMD chip via some support components that are difficult to trace through, so I'll leave it at that.
(D16) is another +5v
(D18) is another ground
And that's it. Nothing to it, really, just some buffers that connect the data lines of the ISA bus directly to the data lines of the IDE bus, plus some mildy complex logic to handle IRQs. I guess this is what PIO transfer mode is all about; I see now why it's so hard on the CPU, since it has to handle all IDE communications directly. (Assuming that's what this card does: PIO) Damn, and it only took me... an hour and a half to trace all that crap. Maybe I'll go to bed. HA!
[edit] spelling
[edit] Information I should have included before:
On an ISA card, the pins are numbered in groups, A, B, C, and D, each group's pin 1 is the pin closest to the mounting bracket.
The 8bit part of the card is A (the front) and B (the back); the 16bit extension is C (front) and D (back). So there.
It was on my desk, so I picked it up.
I had it in my hand, so I looked at it.
I was looking at it, and I wondered just how it worked with only a few simple ICs.
I'm setting to work.
The wiring of this thing is so simple I think I'll just run down the ISA slot and trace each set of pins in general.
On second thought, I'll group 'em logically to some extent. Ah, who cares, you aren't actually going to read this, are you?
The 8 data lines (A2-A9) of the 8bit bus run directly to a SN74LS245N, which is a simple transceiver, and that IC is wired to some of the data lines on the IDE port.
The 8 additional data lines (C11-C18) of the 16 bit extension run directly to another SN74LS245N, which is wired to the remaining data lines on the IDE port. Interesting thing here is, it looks like one 245N handles the odd IDE pins, and the other handles the even. This makes the PCB simpler, plus because of the way IDE ports are laid out, one chip ends up handling IDE data lines 0-7, while the other gets 8-15. So, in summary of these two points, the 16 I/O data lines of the extended ISA bus are essentially connected directly to the 16 data lines on the IDE cable, straight up, bit 0 to bit 0, bit 1 to bit 1, etc.
Moving on....
(A10) leads to a blank drillhole, it goes nowhere on this particular board revision.
(A11) is "address enable" on the ISA bus, and evidently goes high when DMA is in control. It runs to the "output enable" of the most interesting chip on the board, an AMD PALCE20V8H. This thing is some kind of programmable logic, so I shouldn't really try to guess what it does yet.
Ack, things just got weird.
(A22-A30) are address bits (strictly output from the motherboard) on the ISA, and they run directly into appropriate input lines on that interesting AMD chip I just mentioned. Notice that those are only bits 1-9. Bit 0 is strange.
(A31), ISA address bit 0, runs to a SN74LS244N, which is little more than a buffer. (A31)'s signal eventually finds itself at IDE pin 35, which in IDE-eese, is address bit 0. OK, so, while weird, it makes some sense.
Where did it's 9 brethren go? I'll just follow the outputs from the AMD chip and assume that's directly related to them.
Lines from the PALCE20V8H run to:
- IDE pin 1, the IDE reset line
- IDE pin 38, which has something to do with IO address 3F6-3F7, so this has something to do with setting the address at which to find the IDE interface I assume. Strange (to me at least) that that information is actually on the cable.
- one of the 245N's output enable line
- IDE pin 37, another IO address select line, this time 1F0-1F7
- through a capacitor to ground
- to the output enable line of the other 245N
- through a resistor to Vcc
- deadend (absent part)
OK, so that wraps up the goofy, unpredictable chip. Moving on to the B and D ISA pins...
(B1) is ground
(B2) is the system reset trigger, and it runs to capacitor->ground pin on the AMD chip. So the cap may be providing a simple automatic power-on reset command.
(B3) is +5v
(B10) is another ground
(B13) sets I/O write mode on the ISA, and runs through the 244N to IDE pin 23, which is the IDE write mode line
(B14) sets I/O read mode on the ISA, and runs through the 244N to IDE pin 25, which is similarly the IDE read mode line
(B29) is another +5v
(B31) is another ground
(D2) reports a 16bit I/O chip to the motherboard, but I can't figure out where the line goes on this board
(D3-D7) are IRQ request lines for interrupts 10-14, respectively, and with the exceptions of (D5) IRQ 12 and (D7) IRQ 14, they all run to a SN74LS125AN, another buffer. The buffer chip is then connected to the strange AMD chip via some support components that are difficult to trace through, so I'll leave it at that.
(D16) is another +5v
(D18) is another ground
And that's it. Nothing to it, really, just some buffers that connect the data lines of the ISA bus directly to the data lines of the IDE bus, plus some mildy complex logic to handle IRQs. I guess this is what PIO transfer mode is all about; I see now why it's so hard on the CPU, since it has to handle all IDE communications directly. (Assuming that's what this card does: PIO) Damn, and it only took me... an hour and a half to trace all that crap. Maybe I'll go to bed.
HA! [edit] spelling
[edit] Information I should have included before:
On an ISA card, the pins are numbered in groups, A, B, C, and D, each group's pin 1 is the pin closest to the mounting bracket.
The 8bit part of the card is A (the front) and B (the back); the 16bit extension is C (front) and D (back). So there.
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