I don't recall the details, but integrating the memory controller is supposed to make possible a smarter memory access system, which is an important part of boosting performance in the Hammer style Athlon, beyond increasing bandwidth. The decoupled style memory controller meant the CPU and memory system had no information about what either was doing. In addition transfers between the controller and the CPU can now take place at CPU speed ( 2000MHz?), like transfers from cache, rather than the FSB (333Mhz?) This reduces buffering overhead and consequent delays.
Like you say, AMD was constantly waiting for its support companies to get around to implementing what memory technology was capable of. Naturally AMD was always second in line behind Intel as far as VIA was concerned.