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Hyper Transport

jmaniyat

Junior Member
I have been waiting with much anticipation the release of motherboards that support Hyper Transport. From what I have read at Hypertransport.org, this technology will greatly improve data transfer between chips on a board, upto 24X PCI, thereby boosting performance and finally overcomming this common bottleneck. Does any one know or have heard when this technology will reach desktop PCs. NVIDIA has applied this technology on to their nForce chip set but the performance has not been outstanding. I am debating weather to settle on a P4 with a Intel 850 chip set based motherboard or wait for Hypertransport technology.
jm
 
Perhaps I am wrong, but I didn't think the nforce used hypertransport...
The only example of hypertransport i know of is the Xbox....

I would like to know also...

zs
 


<< Perhaps I am wrong, but I didn't think the nforce used hypertransport...
The only example of hypertransport i know of is the Xbox....

I would like to know also...

zs
>>

Too bad all X-Box mobos were recalled...
 
I believe the AMD MPX chipset also incorporates Hypertransport. Unfortunately AMD has no plans to develop single processor chipsets that utilize HT. We will most likely not see this until Hammer. Conversely, VIA's V-link technology is their version of HT, and I believe SiS will have their own bus technology when they move to a North and Southbridge as in their P4 chipset.
 
Just an FYI, there are three high speed connection methods out right now....Hypertransport comes up second to Sis' Multi I/O tecnology. The HS interconnects are as follows:

1. V-Link (Via) 266 mb/s bandwith between NB and SB

2. Hyper Transport (AMD) 566mb/s (supposedly will scale up in the future)

3. Multi I/O (Sis) 1.2 gb/s

🙂
 
The SiS Multi I/O is an onchip solution though, isn't it? AKA, it is not a mobo based bus, but is an internal chipset bus?
 
The hammer (supposedly) comes out in a year and will use up to 3 hypertransports (starting probably with one).

Barton will likely also use hypertransport. It should come out before the hammer (late summer or fall).

Keep in mind that Barton (AMD) and Hammer will have many other improvements in speed in addition to hypertransport technology.
 
The hammer (supposedly) comes out in a year and will use up to 3 hypertransports (starting probably with one).

Barton will likely also use hypertransport. It should come out before the hammer (late summer or fall).

Keep in mind that Barton (AMD) and Hammer will have many other improvements in speed in addition to hypertransport technology.



The reason (Sledge)Hammer has up to 3 hypertransport links is because it can be utilized in a mult-processor board exceeding 2 CPU's (up to 4 total). The first two are used to interface with the other two processors forming the corner of a square, and the final HT link ties the processor to the I/O bus. Clawhammer will undoubtedly not use all HT links as it will be targeted to the single processor market. Let's not forget too that Hammer essentially has two cores, and SMT will likely be available as in the Northwood. Clawhammer chipsets will use Hypertransport with a bus speed of 800MHz and a total bandwidth of 6.4 Giga Byte/s. Three times that of the current 266 MHz EV6 bus.

Barton is the same core as Thoroughbred, but will use SOI wafers. I doubt the motherboard manufacturers will change their chipsets (and their associated bus) if the Thoroughbred is fully compatible with existing V-link and multi I/O technology. They might adapt hypertransport, but unless the benefits are great I wouldn't hold my breath.
 
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