How to improve semiconductor process yield?

[Fjodor2001]

Hi,

There has been a lot of discussions on semiconductor process technology yields lately. So I'd just like to open up this thread to discuss the topic on how that can actually be done to improve that in practice.

Let's say the initial yields are at only 10-20%. Then what changes to the original process can be made to improve that? After all the process yields can eventually reach 50-80% or more with time. That's a really big improvement.

Does the process equipment have to be changed / swapped out? Any steps that can be fine tuned to become more accurate? If someone could give us examples of what changes can be made to improve yield, I think that would be very interesting.

So if you know anything about this, please share it!

 

[witeken]

This: http://www.extremetech.com/extreme/106899-beyond-22nm-applied-materials-the-unsung-silicon-hero

Here's a random quote:

“Further, the ability to analyze that data is critical, he said. “How do you overlay fab monitoring data? When a wafer is going through a fab, there is a lot of data collected on the devices being manufactured. For example, there is a measurement of a width of a line at a specific place on a die. You keep doing that measurement for every wafer that goes through. Those are the inspection machines and metrology machines. How do you collect that data, then correlate it to a particular design attribute that says, ‘After looking at 100,000 die, I know that this particular cell has a marginality because it’s always failing for this particular measurement?’” --Thakar

There are random defects (from tools) and there are systematic ones. Read the full article here: http://semiengineering.com/yield-ramp-challenges-increase/.

 

[Fjodor2001]

Thanks for sharing the articles. Lots of interesting info, but I did not find that much specific details about what was actually done to improve yield unfortunately.

 

[witeken]

Thanks for sharing the articles. Lots of interesting info, but I did not find that much specific details about what was actually done to improve yield unfortunately.

I don't know much else about the topic. If Idontcare (or anyone else) knows something about this, then his comments would be appreciated.

 

[III-V]

http://lmgtfy.com/?q=improving+semiconductor+yields

First result:
http://mouliengg.com/reports/yield_improvement.pdf

 

[NTMBK]

 

[Fjodor2001]

http://lmgtfy.com/?q=improving+semiconductor+yields

First result:
http://mouliengg.com/reports/yield_improvement.pdf

Wow, that simple, huh? You should have sent the link to Intel 1-2 years ago so the could have straightened out their 14 nm yields in time.

 

[III-V]

Wow, that simple, huh? You should have sent the link to Intel 1-2 years ago so the could have straightened out their 14 nm yields in time.

Could a more asinine response have been written?

 

[witeken]

Could a more asinine response have been written?

Yes.

 

[MagnusTheBrewer]

The single biggest improvement could be made by getting the engineers involved in the manufacturing process. The way it works most places today is the engineers analyze failure data and try to correct yields without even understanding the manufacturing process. Think about it, it's like a car mechanic trying to fix a car based on how closely the owner followed the car manual.

 

[III-V]

Yes.

That was a rhetorical question; I wasn't asking for a literal response.

I don't know why the OP refuses to do his own research on these subjects. As I've demonstrated, it's not even remotely difficult -- a simple google search provided incredibly pertinent information as its first result. Surely I am not the only one who tires of the incessant questions from the OP with easily obtainable answers.

The single biggest improvement could be made by getting the engineers involved in the manufacturing process. The way it works most places today is the engineers analyze failure data and try to correct yields without even understanding the manufacturing process. Think about it, it's like a car mechanic trying to fix a car based on how closely the owner followed the car manual.

Do you work in the industry, or is this just a typical armchair engineer observation?

 

[Fjodor2001]

I don't know why the OP refuses to do his own research on these subjects. As I've demonstrated, it's not even remotely difficult -- a simple google search provided incredibly pertinent information as its first result. Surely I am not the only one who tires of the incessant questions from the OP with easily obtainable answers.

Great idea. That way we could kill off 80% of the threads on this forum.

This forum is about the feedback, info and opinions of its members. Sure, links to relevant info can be useful in post. But it does not mean the threads here are useless, even if the some of the info can be found in books or on the Internet. But if you feel otherwise, please go ahead and continue to post links and silly comments all over the place and wreak havoc on the forum.

 

[aigomorla]

optimization of yield takes time.
its not a simple lets lay down template, but a extensively long process from litho to laser cut.

Also ur not going to get any information on fab optimization as its considered a inside trade secret. Intel will not share it, so any amount of research wont net you anything.

Lastly cpu engineers involved the fab processes wont help anything.
They decide on the diagram, and then a fab engineer uses a computer to optimize the layout for litho and processing. This is also why intel doesnt share fabs nor do they sell complete fabs unless that node has been EOL'd.

 

[Mushkins]

Great idea. That way we could kill off 80% of the threads on this forum.

This forum is about the feedback, info and opinions of its members. Sure, links to relevant info can be useful in post. But it does not mean the threads here are useless, even if the some of the info can be found in books or on the Internet. But if you feel otherwise, please go ahead and continue to post links and silly comments all over the place and wreak havoc on the forum.

Anything us forumgoers can possibly say on the subject is no more pertinent than what you can find with a two second google search. If anyone here actually *had* the answer you're looking for, they'd be working for Intel, Intel would be paying them at least six figures, and Intel would be actually using that process (and in turn you'd be able to google how it's done). There's not anything here to discuss or have an educated opinion about, other than stewing in our own ignorance of the subject. Your original question might as well have been "hey guys, how do you turn lead into gold?"

 

[Idontcare]

Let's say the initial yields are at only 10-20%. Then what changes to the original process can be made to improve that? After all the process yields can eventually reach 50-80% or more with time. That's a really big improvement.

Does the process equipment have to be changed / swapped out? Any steps that can be fine tuned to become more accurate? If someone could give us examples of what changes can be made to improve yield, I think that would be very interesting.

Spent my fair share of time working on yield issues. To answer your question the first thing the reader must understand is that in the course of manufacturing a chip the chip itself is going to undergo somewhere in the neighborhood of 400 to 500 separate processing steps.

Every one of which can cause yield issues ranging from nuisance issues that affect parametric yield to bigger issues that affect functional yield to critical issues that affect lifetime reliability.

The cumulative totality of each individual process steps fail adder leads to an overall yield number that you might see come out in the press.

Allow me to give you a numerical example. Let's say you make 20nm semiconductor chips and your 20nm process entails 400 separate processing steps (depositions, litho, etch, cleans, cmp, doping, etc.).

Now let's say you've spent 4 years toiling away to optimize every process at every step in the entire process flow to the tune of having 99.7% yield for each and every given step. Your litho process gives you perfectly printed die with minimal misalignment 99.7% of the time, your deposition processes give you your desired film thicknesses and non-uniformity, as well as particulate and defect free, 99.7% of the time, etc.

Now take that 99.7% perfection and apply it 400 times to your wafer while you make your entire IC. Your 99.7% perfection at any given process step will only result in 30% device yield. (99.7%^400 = 30%)

So you have 30% device yields on your 20nm process flow. So what do you do to make that 30% yield go higher, say to a still meager 45%? Well the answer is, in short, that you have to address each and every one of those 400 process steps in your process flow, you remember the ones which are already optimized to give you 99.7% yield for the given process, and figure out a way to make the yield for that one process go from 99.7% to 99.8%.

And then do that for the remaining 399 steps as well, all so the aggregate effect will be to raise yields from 99.7%^400 to 99.8%^400 (answer: 45% device yield).

Want to take a guess at how difficult, time consuming, and expensive it is to take something that is already very nearly perfect (99.7% is pretty darn close to perfect) and make it just a teeny tiny bit closer to perfect? And then hire enough engineers, give them enough test wafers and access to enough analytical lab resources so as to generate the test data necessary to then feedback into a design of experiments from which a 99.7% yielding process can be incrementally improved to deliver 99.8% yields...

In short, there is a very darn good reason why billions of dollars can be spent, and years of development time afforded to thousands of R&D process engineers, and the device yields will merely be a paltry 20%.

And to improve that yield requires scrutinizing every single step in a multi-hundred step process flow looking for places where a 0.1% yield boost can be found and implemented here or there.

 

[Arachnotronic]

Spent my fair share of time working on yield issues. To answer your question the first thing the reader must understand is that in the course of manufacturing a chip the chip itself is going to undergo somewhere in the neighborhood of 400 to 500 separate processing steps.

Every one of which can cause yield issues ranging from nuisance issues that affect parametric yield to bigger issues that affect functional yield to critical issues that affect lifetime reliability.

The cumulative totality of each individual process steps fail adder leads to an overall yield number that you might see come out in the press.

Allow me to give you a numerical example. Let's say you make 20nm semiconductor chips and your 20nm process entails 400 separate processing steps (depositions, litho, etch, cleans, cmp, doping, etc.).

Now let's say you've spent 4 years toiling away to optimize every process at every step in the entire process flow to the tune of having 99.7% yield for each and every given step. Your litho process gives you perfectly printed die with minimal misalignment 99.7% of the time, your deposition processes give you your desired film thicknesses and non-uniformity, as well as particulate and defect free, 99.7% of the time, etc.

Now take that 99.7% perfection and apply it 400 times to your wafer while you make your entire IC. Your 99.7% perfection at any given process step will only result in 30% device yield. (99.7%^400 = 30%)

So you have 30% device yields on your 20nm process flow. So what do you do to make that 30% yield go higher, say to a still meager 45%? Well the answer is, in short, that you have to address each and every one of those 400 process steps in your process flow, you remember the ones which are already optimized to give you 99.7% yield for the given process, and figure out a way to make the yield for that one process go from 99.7% to 99.8%.

And then do that for the remaining 399 steps as well, all so the aggregate effect will be to raise yields from 99.7%^400 to 99.8%^400 (answer: 45% device yield).

Want to take a guess at how difficult, time consuming, and expensive it is to take something that is already very nearly perfect (99.7% is pretty darn close to perfect) and make it just a teeny tiny bit closer to perfect? And then hire enough engineers, give them enough test wafers and access to enough analytical lab resources so as to generate the test data necessary to then feedback into a design of experiments from which a 99.7% yielding process can be incrementally improved to deliver 99.8% yields...

In short, there is a very darn good reason why billions of dollars can be spent, and years of development time afforded to thousands of R&D process engineers, and the device yields will merely be a paltry 20%.

And to improve that yield requires scrutinizing every single step in a multi-hundred step process flow looking for places where a 0.1% yield boost can be found and implemented here or there.

Thank you for the very enlightening view! :thumbsup:

 

[witeken]

What is the tool manufactures' role in all of this? Can Applied Materials or ASML do anything to make the yield improvement less of a pain for semiconductor companies; why don't they create tools with 100% or 99.9% yield?

 

[Idontcare]

What is the tool manufactures' role in all of this? Can Applied Materials or ASML do anything to make the yield improvement less of a pain for semiconductor companies; why don't they create tools with 100% or 99.9% yield?

That is like asking the company that makes your oven to make the oven such that your cake turns out perfect every single time...and yet the oven has zero control over what you decide to put inside the oven, or inside your cake (ingredients) for that matter.

Tool makers can certainly create crappy tools that prevent you from getting good yields, but they alone cannot make your yields become great.

A crappy oven will pose a challenge to even the finest culinary chefs, but an awesome world-class oven will not turn your mother-in-law's fruit cake into a world-class Michelin restaurant caliber desert

 

[Fjodor2001]

Thanks for the insight!

I was not aware that there were as many as 400 to 500 separate processing steps.

Since that is the case, is there a risk that one or more of those steps will fail to be fine tuned so the yield never reaches above an acceptable level? In that case the whole process technology developed for that node would have to be discarded I assume.

Or is in known beforehand at the research stage that once the process tech has shown proof of concept, it will for sure provide sufficient yield in mass production in factory too, if given enough time to perfect the individual process steps?

I just wonder, because I imagine it would be completely disastrous for a company to completely scrap a process tech for a node. Especially for a company such as Intel that rely on its own process tech and do not consider it an option to transfer production to an external foundry.

 

[witeken]

I think this is more the case in the research and development stage, where you have to build a transistor with the new innovations like HKMG and find a way to implement it in the process. For example, you have gate first and gate last, but there's also a third approach:

Meanwhile, a third approach remarkable in its simplicity emerged. Called fully silicided gates, it lets you follow the normal gate-first process but then lets you turn the polysilicon gate into a metal-silicide gate, essentially replacing every other silicon atom with metal (usually nickel). Then, by doping the nickel silicide, you can alter its work function for use in either an NMOS device or a PMOS one. By late 2006, though, nearly everyone, including us, had given up on the fully *silicided gates approach. No one could move the silicide's work function quite close enough to where it needed to be.

As for the material choices of HKMG, there were many options and of course the most viable, in terms of manufacturing and transistor characteristics, was chosen. So the challenge of finding a better transistor that can be manufactured at high yields seems more like something that happens at an earlier stage.

So that's probably the good thing about this industry, that you have multiple possible solutions:

The event opened with a short course on the challenges of design at 7 nm. The extensive set of talks detailed so many options in areas such as high-mobility channel materials that one researcher said it “shows no one knows what to do.”

For me, the good news is there are many options and lots of smart people checking them out.

 

[Idontcare]

Thanks for the insight!

I was not aware that there were as many as 400 to 500 separate processing steps.

Since that is the case, is there a risk that one or more of those steps will fail to be fine tuned so the yield never reaches above an acceptable level? In that case the whole process technology developed for that node would have to be discarded I assume.

Or is in known beforehand at the research stage that once the process tech has shown proof of concept, it will for sure provide sufficient yield in mass production in factory too, if given enough time to perfect the individual process steps?

I just wonder, because I imagine it would be completely disastrous for a company to completely scrap a process tech for a node. Especially for a company such as Intel that rely on its own process tech and do not consider it an option to transfer production to an external foundry.

Scrapped process nodes are not as rare as you might imagine. GloFo scrapped its 14XM process node in lieu of bringing in Samsung's 14nm process flow. TI scrapped its 45nm process node in lieu of going fabless for 45nm and beyond via TSMC.

Yield is never a given because of the matter of device reliability.

Yield, process flow complexity, and reliability are intrinsically coupled but of the three there is no way you will ever be allowed to compromise on reliability.

So you end up making the process flow ever more complicated not solely because you want your yields to improve, but because you want your yields to improve without sacrificing reliability as doing so would trigger a massive undertaking called a "node requalification" that would entail at least 6 months of zero shippable product.

(note there is a lot more to the story here as I am merely speaking to the perspective of ramping yields in production environment, not convoluting this discussion with a separate topic of yield ramp during process node development where the priorities and project management approach are slightly different)

 

[Idontcare]

I think this is more the case in the research and development stage, where you have to build a transistor with the new innovations like HKMG and find a way to implement it in the process. For example, you have gate first and gate last, but there's also a third approach:

Ugh, FUSI D: What a nightmare that was.

 

[NTMBK]

IDC, what is actually involved in bringing a process in house? Say the GlFo case, switching from 14XM Tto Samsung 14nm. They will use the same wafers and same ASML tools already- by your analogy, they have the same oven and ingredients- so is it the "cookbook" that changes? The order in which they perform process steps, the way in which those steps are carried out?

Thanks for the insights in this thread! As a software guy, it's pretty tricky to understand what you hardware guys get up to- and extremely interesting to find out. :thumbsup:

 

[Idontcare]

IDC, what is actually involved in bringing a process in house? Say the GlFo case, switching from 14XM Tto Samsung 14nm. They will use the same wafers and same ASML tools already- by your analogy, they have the same oven and ingredients- so is it the "cookbook" that changes? The order in which they perform process steps, the way in which those steps are carried out?

Thanks for the insights in this thread! As a software guy, it's pretty tricky to understand what you hardware guys get up to- and extremely interesting to find out. :thumbsup:

Pretty much just a transfer of the "cookbook" as you call it. What gets transferred is the process flow, which is itself a sequence of individual serialized process steps which we really do refer to as "recipes".

Individual process steps (individual recipes) are highly coveted knowledge in commercial espionage, but the pièce de résistance is the process flow itself (sequence of process steps in toto).

The most common way to secure confidential recipe information from your competitors is to work with their tool supplier, as the tool supplier is the most easily influenced piece of the puzzle (they just want to sell more tools, and that can happen easier if you "help" more customers find ways to use your tools ). The second path of least resistance is to hire key employees from your competitors and see if they are a "team player".

Both of those avenues cut both ways, a supplier who is loose with your competitor's confidential information is just as likely to be loose with yours. Same goes for that talkative new hire you just snagged from competitor XYZ.

And of course there are legit ways to secure competitor process information. Sometimes companies will patent their process recipes (a few of mine were), which makes them publicly accessible (but not free to use). It is legal to data mine patents, but you must license the rights to use the patented information if you wish to implement the patents of course.

Which brings us full circle to GF and Samsung's 14nm. In that case GF not only licensed the rights from Samsung to use their patented process recipes, but were also granted licensing access to the entire process flow itself (which is something that is never, ever, patented because it is the crown jewel of the entire 4+ year R&D effort in crafting a process node).

At that point the process of transferring Samsung's 14nm process flow from Samsung to GloFo is no different than the process of Samsung fanning out the node from one internal fab to another internal fab. You electronically transfer the process documents, including recipes, upload to the tools and go about performing your node qual.

 

[witeken]

So yields are the same?