how much L1 cache on pentium 1

[sinthon]

how much L1 cache on pentium 1?

 

[StraightPipe]

i cant remember that far back, i remember that P3 was 512kb

it's probly something ridiculous like 8 hehe

 

[Snooper]

I want to say 32k, but I can't swear to it.

 

[Amorphus]

I'm pretty sure it was 16kb, with up to 2mb COAST

 

[Snooper]

StraightPipe,

You are confusing L2 cache with L1 cache. The max amount of L2 cache was controlled by your chipset and MB manufacturer.

 

[MDE]

8k for code and 8k for data according to an Intel datasheet
ftp://download.intel.com/design/pentium/datashts/24199710.pdf

 

[StraightPipe]

like I said, "i cant remember"

 

[InlineFive]

It might have had none, the K6-2 had no L2 cache...

 

[pm]

It was 8k code, 8k data for a total of 16k. The Pentium w/ MMX increased this to 32k. I remember working on the design of the later Pentiums in the L1I cache.

 

[saltedeggman]

L1 cache > L2 cache....

you guys are missing it up

 

[MDE]

Originally posted by: saltedeggman
L1 cache > L2 cache....

you guys are missing it up

No, L1 is < L2. You're messing it up. I paraphrased an Intel whitepaper, and PM even worked on the chip himself, I think he would know.

 

[thomsbrain]

Originally posted by: StraightPipe
i cant remember that far back, i remember that P3 was 512kb

it's probly something ridiculous like 8 hehe

256 kb on the later ones. i was going to say the code name for the later ones and then i realized i can't even remember that much.

 

[saltedeggman]

Originally posted by: MonkeyDriveExpress

Originally posted by: saltedeggman
L1 cache > L2 cache....

you guys are missing it up

No, L1 is < L2. You're messing it up. I paraphrased an Intel whitepaper, and PM even worked on the chip himself, I think he would know.

i am not refering to size... rather clockspeedwise, and note the thread starter ask for L1 cache

 

[MDE]

Originally posted by: saltedeggman

Originally posted by: MonkeyDriveExpress

Originally posted by: saltedeggman
L1 cache > L2 cache....

you guys are missing it up

No, L1 is < L2. You're messing it up. I paraphrased an Intel whitepaper, and PM even worked on the chip himself, I think he would know.

i am not refering to size... rather clockspeedwise, and note the thread starter ask for L1 cache

Sinthon asked for the size of the L1 cache, IDK where you got clock speed from.

 

[Lonyo]

I have a 256kb cache pipeline burst "stick" for a Pentium 🙂