How long does it take AMD to design and bring a new die variation to market?

[cbn]

In some of my previous threads here here, here and here I asked folks to propose new SKUs for both Intel and AMD.

My particular suggestions (in each thread) happened to based on existing dies. Some other folks ideas would require a new die variation to be made.

However, based on some recent discussions in other threads like this one I am beginning to believe a new die variation might be the best idea for AMD in particular.

So I am wondering just how long would it take AMD to design a new die variation (based on an existing cpu core design) and bring it to market?

 

[cytg111]

Well, they got Keller back in 2012 right? The dude that manifested the K7/K8, layed out Apples Cyclone by hand? With AMD coming back with new archs for 2016 I'd say (pulls out calc) .. 3 to 4 years .

 

[cbn]

Well, they got Keller back in 2012 right? The dude that manifested the K7/K8, layed out Apples Cyclone by hand? With AMD coming back with new archs for 2016 I'd say (pulls out calc) .. 3 to 4 years .

3 to 4 years for a new cpu core design sounds about right.

What I am referring to would simply be a new die variation for an existing cpu core design. (Simple example: Hexcore steamroller of some configuration for an existing AMD socket).

 

[Arachnotronic]

Well, they got Keller back in 2012 right? The dude that manifested the K7/K8, layed out Apples Cyclone by hand? With AMD coming back with new archs for 2016 I'd say (pulls out calc) .. 3 to 4 years .

Do you really think Keller laid out any CPU, by hand, by himself?

 

[.vodka]

Well, he at the very least must have some good influence on the design teams, considering how many successful products have his name written on them.

 

[chrisjames61]

Do you really think Keller laid out any CPU, by hand, by himself?

The man is a certified genius. So yeah.

 

[cbn]

Is six months for a new die variation about how long it takes or is that too optimistic?

 

[TuxDave]

Is six months for a new die variation about how long it takes or is that too optimistic?

Depends on what you're trying to add. Six months can probably get you a frequency bump or some performance impacting bug fixes.

 

[xLegenday]

And hopefully all goes as plan and they dont have to make a new rev

 

[witeken]

Depends on what you're trying to add. Six months can probably get you a frequency bump or some performance impacting bug fixes.

What can you do with SoCs? What could Intel (and Qualcomm, Apple, MediaTek, etc.) do in 6 months? 'Cause that's what Intel want to do: http://intelstudios.edgesuite.net/im/2013/archive/bk/archive.html (28:00).

 

[Idontcare]

What can you do with SoCs? What could Intel (and Qualcomm, Apple, MediaTek, etc.) do in 6 months? 'Cause that's what Intel want to do: http://intelstudios.edgesuite.net/im/2013/archive/bk/archive.html (28:00).

Always a question of budget. Project management triangle and all

 

[Arachnotronic]

The man is a certified genius. So yeah.

AMD promotes hiring Jim Keller in a press release years ago to try to distract investors from its horrific and uncompetitive product lineup, and all of a sudden Keller is a "certified genius" and a "legend"?

There are many incredibly talented architects and engineering managers across the semiconductor industry (including at AMD pre-Keller -- that's why Apple, Qualcomm, and others have been happily poaching from the company). All of them have quietly worked to deliver great products. Only when a company is so desperate to generate PR buzz do they actually waste time telling the world about how this one individual will be a game changer.

Do people not realize that one man doesn't just sit down and make a processor core all by himself?

 

[ShintaiDK]

I would be very anoyed, if I was one of the 500-1000 other AMD engineers working on the project. Just to hear Jim Keller that is a manager now is the god that sole handed creates the CPU(s) and dictate any success or not.

And rememebr Keller left AMD in 1999. Long before their K8 success.

 

[Fjodor2001]

And Steve Jobs was also only one guy, so he meant nothing for Apple?

 

[john5220]

Question

How difficult is it to design these processor cores?

Like what I mean is for each of the 1 billion transistors is there a different mathematical equation? like calculus or something? and does the 100 million have to line up and the equation have to be correct for the 1 billionth?

 

[cbn]

Depends on what you're trying to add. Six months can probably get you a frequency bump or some performance impacting bug fixes.

Is that what is normally called a stepping?

I was actually thinking of AMD not even touching the cpu cores/modules and instead just rearranging the location of modules to make a new die configuration.

I think if there were two posts that sum up my feelings for new AMD dies at this moment it would be these two:

http://forums.anandtech.com/showpost.php?p=37044686&postcount=59

If a person thought 3M/6T Steamroller or 3M/6T Excavator would interfer with 4M/8T Piledriver, I'd imagine AMD could release two dies:

1. 3M/6T Steamroller or Excavator die without L3 cache for value enthusiast.

2. 5M/10T Steamroller or Excavator die with L3 cache for servers and higher end enthusiasts

Of course, these would be for AM3+.

http://forums.anandtech.com/showpost.php?p=37044749&postcount=60

For a FM2+ SKU, If AMD ever went Hexcore I would hope they would only include a very minimum iGPU. (1 CU/64 GCN streamprocessors max). This to help them undercut Intel on cost.

With that said, I still think Hexcore is probably better off on AM3+. This way a person has the choice of integrated graphics or not via the chipset rather than having every processor die having the costing adding iGPU on it.

For the mainstream budget desktop enthusiast, I feel AMD's performance is not bad. However, the major problem I see appears to be high cost to manufacture related to either high amounts of die bloating L3 cache on the AM3+ Piledrivers or high amounts of die bloating iGPU on the FM2+ Kaveri. Some type of lean and mean hexcore variant could fix both weaknesses.

Same goes for whatever AMD is planning for Zen. I would like to see some lean and mean die variant of that aimed at the value mainstream desktop user that is relatively cheap to produce. This so AMD can afford to get into a price war with Intel (who is focusing on adding lots of die bloating iGPU on their mainstream LGA 115x chips) if necessary.

P.S. With respect to large iGPUs (in general), I feel they are better suited for mobile SKUs only.

 

[witeken]

Question

How difficult is it to design these processor cores?

Like what I mean is for each of the 1 billion transistors is there a different mathematical equation? like calculus or something? and does the 100 million have to line up and the equation have to be correct for the 1 billionth?

I don't know any details, but

1) There's a lot of duplication going on: multiple cores, SRAM cells, graphics etc.
2) Some things only have to be designed once (unless they want to optimize it)
3) Many things are the result of many updates
4) There's also a lot of computer aid

But it still takes about 4-5 years to design a bleeding edge core like Haswell (P4 was 4.5 years), so it isn't an easy task. The validation is also pretty scary I guess, since you want to avoid critical bugs that can cause many millions of dollars if you only catch them after release.

 

[cbn]

Here is the current Vishera die:

(315mm2 on GF 32nm, four modules and 8MB L3 cache)

If that L3 cache were gone, that die would be so much smaller.

Now imagine how large a three module AM3+ Steamroller without L3 cache on GF 28nm would be? I'm guessing around 100mm2 +/-. (which is about the same size as socket AM1 SOC)

 

[cytg111]

Do you really think Keller laid out any CPU, by hand, by himself?

No, he was problary hired as a pretty face.. U know, marketing.

AMD promotes hiring Jim Keller in a press release years ago to try to distract investors from its horrific and uncompetitive product lineup, and all of a sudden Keller is a "certified genius" and a "legend"?

Yes, much like Jesus Christ was not recognized by his peers at the actual time of events, he was later posthumous recognized as the son of god. Difference being Jim is not dead.

bzzzztusualamdfudbzzzzt

Yes I see, very interesting.



... Common, stay on the friggin topic instead of putting "the aspergers" on display. Again. So Keller is a talented individual, you cant let him have that cause he used to work for a company you happen to dislike. Whatever.

 

[ShintaiDK]

Now imagine how large a three module AM3+ Steamroller without L3 cache on GF 28nm would be? I'm guessing around 100mm2 +/-. (which is about the same size as socket AM1 SOC)

Kaveri is 246mm2. AMD says 47% is for the GPU. So a GPU-less Kaveri with 2M4T would be around 130mm2.

 

[cbn]

Kaveri is 246mm2. AMD says 47% is for the GPU. So a GPU-less Kaveri with 2M4T would be around 130mm2.

Here is die shot of Kaveri:

First off, the two Steamroller modules with their L2 cache look so much smaller than the iGPU. It almost looks like four modules with their L2 cache could fit in that 115mm2 iGPU space making each module something around ~30mm2

And doesn't Kaveri have components on die that would be located separately on the AM3+'s chipset? Furthermore, regarding the size of the Kaveri DDR3 PHY, I'd have to imagine that would be much reduced in size if the iGPU were gone.

Therefore I don't think simply subtracting iGPU die size real estate from Kaveri gives us an estimate of what an AM3+ SR die size would weigh in at.

 

[ShintaiDK]

Here is die shot of Kaveri:

First off, the two Steamroller modules with their L2 cache look so much smaller than the iGPU. It almost looks like four modules with their L2 cache could fit in that 115mm2 iGPU space making each module something around ~30mm2

And doesn't Kaveri have components on die that would be located separately on the AM3+'s chipset? Furthermore, regarding the size of the Kaveri DDR3 PHY, I'd have to imagine that would be much reduced in size if the iGPU were gone.

DDR would be the same. The only part really is to replace the 20 PCIe lanes, x16+A-link Express with Hypertransport links. And the HT link speed is slower than Kaveris PCIe solution.

So you still end up with a much larger die than you estimate. 160-170mm2 or more. Quite far from 100mm2. And you may have to add L3 due to interconnect, caches etc.

 

[cbn]

DDR would be the same.

Here is a die shot of Vishera:

Granted, this is 32nm.....but the area allocated to DDR3 PHY looks far smaller proportionally than what we are seeing on Kaveri.

 

[ShintaiDK]

On the 32nm vishera you link, the DDR controller takes up roughly 10% of the die. Or 30mm2 or so.

 

[cbn]

In fact, even comparing the Kaveri DDR3 PHY size to the Trinity DDR3 PHY size (scaled 28:32) shown below in the chip architect diagram below, I would say the Kaveri DDR3 PHY is about twice the area of the Trinity DDR3 PHY: