How is the next manufacturing node determined?

[chubbyfatazn]

How did Intel/AMD/whoever else determine that the next manufacturing node is 22nm, from 32nm? I don't quite understand why it went, for instance, from 180-130-90-65-45-32-22-16nm. Is that the closest they can foresee themselves getting two transistors together in the development time they have? Or the fabs' capabilities themselves?

And why is it different for GPUs? I've seen GPUs fabbed on 130/90/65nm, but also 110/80/55/40/28nm. Thanks for any replies.

 

[ShintaiDK]

28nm is the halfnode of 32nm. Also called an optical shrink. Its not as effective as a real node switch. Mainly cost savings.

The 32->22nm are because they double the capabilities. And its decided that its the most economicly way to do it. You could call it Moores law. Every 2 years, double the transistor budget.

 

[Maximilian]

Why is it that 22nm is double the capacity of 32nm? Im sure im missing something but wouldnt 16nm be double 32nm?

 

[Ferzerp]

You have to square it (features are 2d, not 1d). 32^2 = 1024, 22^2 = 484. They aren't exactly 2x, but the shrink typically allows 2x features in the same area.

 

[ShintaiDK]

Why is it that 22nm is double the capacity of 32nm? Im sure im missing something but wouldnt 16nm be double 32nm?

Try think in area rather than length :biggrin:

For example 22*22 vs 32*32.

 

[Maximilian]

Oh i get it! Durr

 

[chubbyfatazn]

So each shrink is generally half the size of the last process? I'd do the calcs, but I don't want to look more busy than I already am...

 

[AtenRa]

28nm is the halfnode of 32nm

28nm HKMG TSMC's process is full node over TSMC's 40nm bulk process.

GloFo's 28nm was supposed to be a half node process over their 32nm SOI HGMK but i have no idea if they haven't changed that.

 

[AtenRa]

The number of the process defines the actual Gate length now days. That means it is the length of the gate of each transistor manufactured with this process. Usually we get close to double (2x) the transistor density with every full node shrink process.

Intel always using a full node bulk process for its CPUs, GPUs where using both Full node and Half node processes. But it seems TSMC will skip the half nodes from now on.

 

[Puppies04]

So each shrink is generally half the size of the last process? I'd do the calcs, but I don't want to look more busy than I already am...

Not quite, as ferzerp already pointed out it is more about fitting more transistors in less space. IB dies are roughly 75% of the size of SB but has 20% more transistors (rough counts) hence the increased teperatures even though the voltage is lower.

 

[Ferzerp]

Basically, a "full node" shrink is [current size]/sqrt(2)

 

[pm]

In addition to all the other good answers, there is an industry consortium that exists to align everyone together.
http://www.itrs.net/reports.html

Click on a year and then lithography and you can see the roadmap going forward.

 

[taltamir]

How did Intel/AMD/whoever else determine that the next manufacturing node is 22nm, from 32nm? I don't quite understand why it went, for instance, from 180-130-90-65-45-32-22-16nm. Is that the closest they can foresee themselves getting two transistors together in the development time they have? Or the fabs' capabilities themselves?

its actually all marketing. They pull those numbers out of their hindquarters and they are meaningless.
Also different manufacturers on the same number are vastly different. For example, if you compare an intel node to a same named node by another manufacturer the intel node is actually equivalent to their next gen node..

That is, intel 45nm is equivalent to TSMC 32nm in transistor density. And that is not counting innovations like highK metal gates and trigate and the like.

 

[Don Karnage]

I can't wait for Broadwell