Uhh, come again? This is latency we're talking about, not bus speed. With a lowered latency of 25%, the processor will, on average, wait 25% less per memory read than with a CAS of 2.5. This does not affect the speed of burst reads (afaik, correct me if I am wrong), but I don't see how the internal doubling of DDR is related to the percentile gain in performance .. 25% is 25% regardless of how many intervals you divide over.