apoppin
Lifer
i hope this wasn't posted - it's from yesterday. 😛
i found it rather interesting and a "history lesson" and a probable look into the near future . . . here are a few excerpts:
We may need it for Office 2060. Back to the future
[edited]
UltraLarge Memory - hidden Opteron advantage?
As X86 architecture is now fully in its 64-bit phase and who would've thought of it in 1980, looking at the clumsy 808, it can address lotsa memory if given a chance to - surely that's good for supercomputing, large databases, future super-duper games or 3-D simulations.
The current dual-CPU Xeon64 chipsets provide for four to eight slots of RAM, which, if using the 2GB registered DDR2-400 DIMMs, provide you with up to16 GB on-board memory - not bad for a start. For dual Opterons, same story - if using 4GB registered DDR DIMMs, you get 32 GB RAM right now. On quad-Opterons and quad-CPU Potomac XeonMP systems, there are usually four channels of memory, each with four DIMM sockets, unless some kind of bridging is used to enhance the memory capacity at the cost of higher latency, so the capacity doubles.
But what if we need even more memory, yet no more CPUs? After all, many large computing jobs may be happy with certain fixed computing power, but as large as possible RAM - database searches, proteonics, high-resoluting weather models or computational chemistry come to mind.
On Xeons, well, we could either make memory controllers with more channels, use bridges translating one memory channels into two, or wait for FB-DIMM generation with more channels anyway.
What about Opterons? The integrated dual-channel memory controller limits you to four DIMMs if using DDR400 timing, or up to eight DIMMs with DDR333 / 266 timing (see HP Proliant DL585). This way, a four way Opteron could have 64 GB of DDR400 or 128 GB of slower DDR memory on board. Then?
Well, each 8xx series Opteron CPU has three HT channels (currently supported at 1 GHz for 8 GB/s data rate per channel). In a quad-CPU configuration, let's say two channels go to the two neighbouring CPUs, so one channel is free on each CPU. Let's say then that one channel on CPU 0 and one channel on CPU 2 go to the I/O through respective PCI-X and PCI-E HT bridges and tunnels (sounds as if we're talking about a highway). This gives us 16 GB/s of total I/O bandwidth, more than enough for any current dual-GPU workstation, server or even 'distributed shared memory' tight cluster wit, say, multiple Quadrics rails.
[edited]
In the near future, with new Opteron sockets, and more & faster HT 2.0 channels (after all, AMD could easily put up to 6 HT channels on a next-generation high-end Opterons for greater SMP, I/O and memory scaling), this approach would make even more sense.
And for now, just imagine, 192 GB RAM with very respectable bandwidth in a standard 3U quad-CPU box! A great deal for memory-intensive HPC or database clusters, and hey, this much RAM will probably be enough even for the near-future 64-bit MS Office too, no matter how bloated that one is expected to be...[/quote]
i found it rather interesting and a "history lesson" and a probable look into the near future . . . here are a few excerpts:
We may need it for Office 2060. Back to the future
[edited]
UltraLarge Memory - hidden Opteron advantage?
As X86 architecture is now fully in its 64-bit phase and who would've thought of it in 1980, looking at the clumsy 808, it can address lotsa memory if given a chance to - surely that's good for supercomputing, large databases, future super-duper games or 3-D simulations.
The current dual-CPU Xeon64 chipsets provide for four to eight slots of RAM, which, if using the 2GB registered DDR2-400 DIMMs, provide you with up to16 GB on-board memory - not bad for a start. For dual Opterons, same story - if using 4GB registered DDR DIMMs, you get 32 GB RAM right now. On quad-Opterons and quad-CPU Potomac XeonMP systems, there are usually four channels of memory, each with four DIMM sockets, unless some kind of bridging is used to enhance the memory capacity at the cost of higher latency, so the capacity doubles.
But what if we need even more memory, yet no more CPUs? After all, many large computing jobs may be happy with certain fixed computing power, but as large as possible RAM - database searches, proteonics, high-resoluting weather models or computational chemistry come to mind.
On Xeons, well, we could either make memory controllers with more channels, use bridges translating one memory channels into two, or wait for FB-DIMM generation with more channels anyway.
What about Opterons? The integrated dual-channel memory controller limits you to four DIMMs if using DDR400 timing, or up to eight DIMMs with DDR333 / 266 timing (see HP Proliant DL585). This way, a four way Opteron could have 64 GB of DDR400 or 128 GB of slower DDR memory on board. Then?
Well, each 8xx series Opteron CPU has three HT channels (currently supported at 1 GHz for 8 GB/s data rate per channel). In a quad-CPU configuration, let's say two channels go to the two neighbouring CPUs, so one channel is free on each CPU. Let's say then that one channel on CPU 0 and one channel on CPU 2 go to the I/O through respective PCI-X and PCI-E HT bridges and tunnels (sounds as if we're talking about a highway). This gives us 16 GB/s of total I/O bandwidth, more than enough for any current dual-GPU workstation, server or even 'distributed shared memory' tight cluster wit, say, multiple Quadrics rails.
[edited]
In the near future, with new Opteron sockets, and more & faster HT 2.0 channels (after all, AMD could easily put up to 6 HT channels on a next-generation high-end Opterons for greater SMP, I/O and memory scaling), this approach would make even more sense.
And for now, just imagine, 192 GB RAM with very respectable bandwidth in a standard 3U quad-CPU box! A great deal for memory-intensive HPC or database clusters, and hey, this much RAM will probably be enough even for the near-future 64-bit MS Office too, no matter how bloated that one is expected to be...[/quote]
