How does the 865/875 access the memory?

[Mingon]

The P4 fsb is made up of 4 transfers per clock, with the dual channel motherboard does it use either 2 64bit channels or 1 combined 128bit channel for memory transfer?

Does the first memory bank transfer data on the first 2 fsb transfers and the second memory on the third and fourth? I am just wondering how 'synchronus' it actually is i.e ddr memory is twice per clock cyle, so 2 channels should be able to match the 4 transfers of the fsb if the timing is triggered 1/2 of a clock cycle later for 1 bank.


(Not sure I have worded this question right, if it makes no sense just ignore)

 

[stardust]

its 2x 64bit channels run simultaneously...it should but couldn't technically be called 128 because of speed issues

but nby simultaneously i mean per clock cycle...so up for banks 1 and 3, down for banks 2 and 4....ehh im not too sure myself