AMD achieves 200 MHz FSB by transfering data on both rising edges and falling edges. That makes sense. But how about quad bump a 100FSB to 400 FSB on Intel's NetBurst architecture? How do they do that?
How does quad bumping in Intel Pentium 4 work?
- Thread starter vtqanh
- Start date
Adul
Elite Member
the only way I can figure out how is that they transmit at the top and bottom edges of the clock signal. So you can get 4x from that. Otherwise I am not total sure on how.
I believe it is quad pumping and I'm pretty sure adul is right.
They get four readings per cycle. If you look at a square wave, basically they move data every 90 degrees.
Just the way DDR memory works except with it you get two "ticks" per cycle.
They get four readings per cycle. If you look at a square wave, basically they move data every 90 degrees.
Just the way DDR memory works except with it you get two "ticks" per cycle.
Just went over the AGP 3.0 specs in the other thread. It has a X8 transfer ability. The specs are both Intel so the underlying techniques are possibly the same.
In the AGP x8 scheme, it is basically simple. They make the data lines very busy. Eight bits per 66mhz AGP period. A date line would look like a 233mhz square wave if the data alternated 1's and 0's. That will get you 466 megabits / second on each line. To reduce the power consumption of such a fast buss, they also reduce the voltage swing to 0 / 0.8 volts for the data states.
If the scheme is the same with the "quad pumped" 100mhz buss, it would get you 200mhz square waves with alternating 1's and 0's and 400 mbits per second per line.
Easier said than done, but in principle, just binary coding.
In the AGP x8 scheme, it is basically simple. They make the data lines very busy. Eight bits per 66mhz AGP period. A date line would look like a 233mhz square wave if the data alternated 1's and 0's. That will get you 466 megabits / second on each line. To reduce the power consumption of such a fast buss, they also reduce the voltage swing to 0 / 0.8 volts for the data states.
If the scheme is the same with the "quad pumped" 100mhz buss, it would get you 200mhz square waves with alternating 1's and 0's and 400 mbits per second per line.
Easier said than done, but in principle, just binary coding.
DDR works by a transfer of a bit at the rise as well as the fall of a cycle.
intel's quad pump for their p4 does 2 bits at rise and then 2 more at the fall, i think. this is also how intel is going to get 533, by 4x133.
intel's quad pump for their p4 does 2 bits at rise and then 2 more at the fall, i think. this is also how intel is going to get 533, by 4x133.
<< the only way I can figure out how is that they transmit at the top and bottom edges of the clock signal. So you can get 4x from that. Otherwise I am not total sure on how. >>
Isn?t RD RAM quad pumped and double data rate (thus PC800)? If so, wouldn?t quad pumping have to be something other than transmitting on the rising and falling edges of the clock?
Or am I just totally confused?
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