How does Intel bin their chips?

[Hulk]

Does anyone know what type of testing Intel does to bin their chips? It must be fast and accurate considering the number of chips they move.

And what do they do once the yields are good on a particular core? For example, right now it seems most Core 2 Duo's can reach 2.93GHz, the speed of the current top of the line for this chip, how do they determine which cores will be spec'd to run at which speeds?

Say there are a few small amount of "duds." Chips that only go to 2.1 or 2.2GHz. Wouldn't those chips automatically be E6300's?

Are the "best" cores, the ones that go high on low voltage binned for mobile use?

I know this is all super secret stuff I'm just wondering if anyone has any ideas about this. I find it very interesting.

 

[Idontcare]

Binning is not a super-secret phenomenon, binning parameters to bin parts in less time with less capital investment in probers and such of course would be OEM dependent as that is a competitive advantage in this industry.

Do some googling for schmoo plots. They are a good start for understanding the basics of where and how binning starts.

 

[lenjack]

Classified...national security...You want to live, don't you?

 

[pm]

There's been some good articles in previous issues of the Intel Technology Journal - I remember one covered the process thoroughly. But I can't seem to find that article - it was an older one... like late 90's. I tried to find it but couldn't. If I remember - and anyone is interested - I'll see if I can't dig up an external page link using the internal search engine.

This one goes through the flow:
http://www.intel.com/technology/itj/q32000/pdf/thermal.pdf

It's specifically on thermal issues during test, but it covers sort, burn-in and class - which are the main stages.

Beyond that article, binning occurs during a section of testing called "class" (at Intel anyway). Class uses a very large (rather expensive) type of component tester - usually most companies use Agilent Advantest, Credence Duo, Schlumberger 9000, or Teradyne Catalyst testers for this stage. In a nutshell, think big (like the size of a minivan) expensive (think 10's of millions of $US) and heavily automated with a computer screen on one side and place to load and remove trays of CPUs on one end. A test suite is written for the CPU by the designers of the chip and is loaded into the tester. These tests are a like chunks of assembly code crafted to stress portions of the chip. Parts are tested at various voltages and temperatures looking for where the part begins to fail. Using this data, extended life testing data (simulates a CPU over a long period - like 10 years), and a lot of statistics, a bin program is developed and the testers then basically work through a testing flow and "drop" parts into various bins depending on where in the program they fail. This determines their final ship speed.

There's a discussion of some of the statistics in this ITJ article, on page 333:
http://www.intel.com/technology/itj/200...ssue04/art07_datamining/vol8_art07.pdf

Shmoo plots are generally used in debug. The tester flow doesn't test all points like you would do in a shmoo but uses a smaller selection chosen to ensure high throughput.

Patrick Mahoney
Senior Design Engineer
Intel Corp.

 

[Hulk]

Wow. Great info.

Thanks.

 

[MmmSkyscraper]

Originally posted by: Hulk
Wow. Great info.

Thanks.

:thumbsup:

 

[Roguestar]

There you have it, kids. Straight from the horse's mouth. Thanks PM!

 

[Yellowbeard]

One thing to keep in mind too that Intel does not necessarily sell every core at the speed at which it was binned. In the past, supply and demand plays into it. You can bet that the demand is WAY higher for the E6300 as opposed to the E6700 and E6800. So, if the fabs don't turn out enough cores suitable for an E6300, then other faster cores can be down binned and sold. Intel will not let silicon sit still for long.

This was VERY common in the early Northwood 800mhz days. That's part of the reason why so many people got 2.4c CPUs that would run 3ghz+ on stock Vcore.