Originally posted by: Bassyhead
Think of a CPU pipeline as an assembly line. Depending on how fast or slow things are moving along, some of the stages along the assembly line might not be doing anything. We can create a second "virtual" assembly line that uses those idle stages. Basically how hyperthreading works is that Intel takes advantage of the fact that many pipeline stages will have idle time here and there. This wouldn't work well on a CPU with less pipeline stages like any AMD Athlon CPUs.
No!
An instruction must progress through the
entire pipeline. Instructions from other threads cannot skip pipeline stages to fill in 'idle stages'.
The point of Hyperthreading is to keep the
execution units busy. By providing the schedulers with two
independent instruction streams (threads) to pick instructions from, the chances of the schedulers not being able to find instructions that can be executed in parallel are reduced, and therefore so are the chances of having idling execution units.
Execution width determines suitablility for SMT, not pipeline depth!
Regarding the Athlon 64, it is in my opinion a good candidate for SMT. It is able to decode three instructions per clock, but is only able to sustain an average IPC of three
if its Out-Of-Order engine can find three instructions to execute in parallel every clock cycle, which is rarely the case.
With the advent of multicore processors, the importance of core-level SMT has been reduced, certainly from a multitasking perspective.
An often overlooked (or unknown) fact is that the main reason Intel introduced Hyperthreading is not to address any design weakness of the P4, but to encourage software developers to start writing multithreaded applications, allowing performance to scale with additional cores in the future.
