Can anyone please explain to me how the Pentium III or Athlon works, in detail, and if so and if applicable include your credentials. It would be cool if you could post it, but if you feel like not posting it, then you can send it to SXMP4@home.com . I really greatly appreciate it, as I need to be able to explain how a processor works, and am hung up at the point to which I am only thinking of processors as being binary, and I know that not to be the case. (I think=) As you can see, I need some help. I know all the basics, so please someone, or at least point me in the direction of some information. Thnx in advance.
How does a processor work?
- Thread starter SXMP
- Start date
Bleh, this question is just as general as asking how the world works. You might want to go to your local library and pick up some books on the topic. Pick up some computer architecture books. You'll see that it covers mulititudes of aspects from electrical currents to data structures to adders/multiplexors, etc. List goes on...
Well, they are binary. The cpu is made up of millions of transistors. Each acting like a on/off switch, or more accurately, a 1/0 switch. Put a couple in series or parallel, and you get logic gates.
But, as for your question, you ought to clarify. Are you asking how the logic of a cpu works or how it physically/eletronically works?
--John Rembecki
Fab Technician
Intel Corp.
But, as for your question, you ought to clarify. Are you asking how the logic of a cpu works or how it physically/eletronically works?
--John Rembecki
Fab Technician
Intel Corp.
This is, as the other posters suggested, a very broad question.
I'd be happy to answer your question, but they are devices with literally millions of transistors in them, that take years to design, and you could take a couple of semesters of college classes on VLSI design and still not completely understand all details of how a CPU works.
What specifically did you want to know?
Intel's web museum site here has a good intro (look on the left-hand side frame and choose "How Microprocessors Work"
. If this is too basic, I can recommend several college textbooks that go into a lot more detail. Several websites have HTML intros that are somewhere between the Intel and the college level discussions, but I'd have to look around for links.
Patrick Mahoney
IPF (McKinley) Microprocessor Design Engineer
Intel Corp.
I'd be happy to answer your question, but they are devices with literally millions of transistors in them, that take years to design, and you could take a couple of semesters of college classes on VLSI design and still not completely understand all details of how a CPU works.
What specifically did you want to know?
Intel's web museum site here has a good intro (look on the left-hand side frame and choose "How Microprocessors Work"
. If this is too basic, I can recommend several college textbooks that go into a lot more detail. Several websites have HTML intros that are somewhere between the Intel and the college level discussions, but I'd have to look around for links. Patrick Mahoney
IPF (McKinley) Microprocessor Design Engineer
Intel Corp.
that's a very broad question, what specifically would you like to know?
How basic/advanced of an explanation are you looking for?
Off hand, I'd suggest purusing Ace's Hardware for some of their technical articles, they have some extremely good articles there.
How basic/advanced of an explanation are you looking for?
Off hand, I'd suggest purusing Ace's Hardware for some of their technical articles, they have some extremely good articles there.
Hehehe, yeah, how down and dirty do you want to get?
Here's a brief overview of MIPS-RISC architecture (simply because it's much easier to describe than x86) from a high-level view:
When you write code in C++ or any high-level language, it gets translated into assembly. These simple instructions are those directly recognized by a CPU, and called the instruction set. For MIPS-RISC, there are (off the top of my head) the following formats of instructions:
R-type: ALU operations (add, subtract, bit-wise logical) and load/store to/from memory
I-type: Similar to R-type but using an immediate value
Branch: conditionally jump to an instruction address
Jump: unconditionally jump to an instruction address
If you have any programming experience, you would know branch and jump operations from conditional statements. High-level statements such as if, while, for, etc. are translated into branch instructions.
Also, whereas high-level languages often use variables located in main memory, MIPS-RISC uses registers for most of its operations. Registers are internal flip-flops that can store data, and have the advantage over memory that they can be accessed in the same clock cycle they are needed. For example, the add operation:
add $2, $5, $7
means add registers $5 and $7 and store the result in register $2. These registers are grouped in what is called the register file.
This sequence of assembly instructions are translated into binary by the assembler and stored in the instruction memory. Each line in assembly gets translated to a single instruction. Now we get into the internals of the CPU.
The following explanation is for an R-type or I-type instruction of a multicycle processor, which takes multiple clock cycles to complete an instruction. In between each physical part of the CPU is a latch that stores the results and control signals from the previous cycle.
The CPU has a register called the PC (Program Counter) which contains the address of the instruction to be executed. This address is fed into the instruction memory, which outputs the current instruction. Also, the PC gets incremented by 4, so that the next instruction will be called when needed. This cycle is called instruction fetch.
The next cycle is called instruction decode/register fetch. First, the instruction is sent to what is called the control unit. It reads the instruction and determines what type of instruction it is. Based on this, it turns on the proper control signals to the various multiplexors (they select between a number of inputs) and the ALU (arithmetic logic unit), so that the proper instruction is executed. Also during this cycle, the addresses of the of the registers to be accessed are sent to the register file.
The next cycle is execution. With the proper signals from the register file sent to the two inputs of the ALU, the ALU operation, such as add, subtract, and, or, shift, etc. is performed.
The following cycle is memory access, during which the contents of a register are either stored into the data memory, or a data/address is accessed from the data memory.
The following cycle is write back, when the results of an ALU operation or memory access are stored into the register file. Next cycle, the PC register will contain the address of the next instruction to be executed, and the process starts over.
In the case of a branch or jump instruction, the address is calculated from an immediate value (in the case of jump) or an offset (in the case of branch) and stored into the PC register. Thus, instead of sequentially executing the instructions in the instruction memory, a jump or branch instruction will jump to some other instruction other than the next one.
All of these structures described are implemented using logic gates, such as AND, OR, NOT, etc. Using a number of inputs that can have a high voltage (logic 1) or a low voltage (logic 0), the output is formed. These gates in turn can be implemented using transistors. How the actual structures of the CPU are designed from logic gates is much more complex...it would be best if you read this from a book.
As for credentials, I'm a CS (and physics) major, and I'm taking a microprocessor design class.
Here's a brief overview of MIPS-RISC architecture (simply because it's much easier to describe than x86) from a high-level view:
When you write code in C++ or any high-level language, it gets translated into assembly. These simple instructions are those directly recognized by a CPU, and called the instruction set. For MIPS-RISC, there are (off the top of my head) the following formats of instructions:
R-type: ALU operations (add, subtract, bit-wise logical) and load/store to/from memory
I-type: Similar to R-type but using an immediate value
Branch: conditionally jump to an instruction address
Jump: unconditionally jump to an instruction address
If you have any programming experience, you would know branch and jump operations from conditional statements. High-level statements such as if, while, for, etc. are translated into branch instructions.
Also, whereas high-level languages often use variables located in main memory, MIPS-RISC uses registers for most of its operations. Registers are internal flip-flops that can store data, and have the advantage over memory that they can be accessed in the same clock cycle they are needed. For example, the add operation:
add $2, $5, $7
means add registers $5 and $7 and store the result in register $2. These registers are grouped in what is called the register file.
This sequence of assembly instructions are translated into binary by the assembler and stored in the instruction memory. Each line in assembly gets translated to a single instruction. Now we get into the internals of the CPU.
The following explanation is for an R-type or I-type instruction of a multicycle processor, which takes multiple clock cycles to complete an instruction. In between each physical part of the CPU is a latch that stores the results and control signals from the previous cycle.
The CPU has a register called the PC (Program Counter) which contains the address of the instruction to be executed. This address is fed into the instruction memory, which outputs the current instruction. Also, the PC gets incremented by 4, so that the next instruction will be called when needed. This cycle is called instruction fetch.
The next cycle is called instruction decode/register fetch. First, the instruction is sent to what is called the control unit. It reads the instruction and determines what type of instruction it is. Based on this, it turns on the proper control signals to the various multiplexors (they select between a number of inputs) and the ALU (arithmetic logic unit), so that the proper instruction is executed. Also during this cycle, the addresses of the of the registers to be accessed are sent to the register file.
The next cycle is execution. With the proper signals from the register file sent to the two inputs of the ALU, the ALU operation, such as add, subtract, and, or, shift, etc. is performed.
The following cycle is memory access, during which the contents of a register are either stored into the data memory, or a data/address is accessed from the data memory.
The following cycle is write back, when the results of an ALU operation or memory access are stored into the register file. Next cycle, the PC register will contain the address of the next instruction to be executed, and the process starts over.
In the case of a branch or jump instruction, the address is calculated from an immediate value (in the case of jump) or an offset (in the case of branch) and stored into the PC register. Thus, instead of sequentially executing the instructions in the instruction memory, a jump or branch instruction will jump to some other instruction other than the next one.
All of these structures described are implemented using logic gates, such as AND, OR, NOT, etc. Using a number of inputs that can have a high voltage (logic 1) or a low voltage (logic 0), the output is formed. These gates in turn can be implemented using transistors. How the actual structures of the CPU are designed from logic gates is much more complex...it would be best if you read this from a book.
As for credentials, I'm a CS (and physics) major, and I'm taking a microprocessor design class.
I liked that link PM.. I just searched and searched but couldn't find anything on the AMD site about it.. how come athlons have so many more transistors than PIII's???
How many do Athlons have?
EDIT:
"The new Thunderbird features a 37 million transistor core" --AnandTech
EDIT:
"The new Thunderbird features a 37 million transistor core" --AnandTech
Thanks, I knew there's a reason that I'm taking that class.
The Athlon probably has more transistors due to its 128KB L1 cache.
The Athlon probably has more transistors due to its 128KB L1 cache.
Sohcan
are you using a book called "computer organization and design: the hardware/software interface" by patterson and hennessy? just curious.
are you using a book called "computer organization and design: the hardware/software interface" by patterson and hennessy? just curious.
cuz ucla is using that book for the cs151b course i'm taking here. they used it at berkeley as well i believe. my friend's professor up there wrote it or something like that. the mips-risc model was a dead giveaway. small world =)
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