One of the guys here just finished his PhD thesis and was recruited by Intel for his work. Basically, there are two things that make CPUs very difficult to produce repeatably: wafer formation and transistor formation.
Wafer formation is carried out under very specific conditions such that the flows are controlled by the solution surface tension (the name of this kind of flows escapes me at the moment). This is the case because, under 'normal' (gravity-driven) flows, a wafer of non-uniform thickness would result.
Transistor formation in the future (not exactly sure how it's done now 😛) will be carried out as a self-assembly process. Given specific conditions (temperature, pressure, concentration of various species), one can predict the formation of crystals very well using mesoscale simulations. I have a thesis on this type of work for anyone who is interested, though it's pretty lengthy (282 pages).
Edit: So, to answer the OP's question, models for these things are still under development. Much of the work done is empirical, so they naturally improve the control of important process variables over time. Every time you shrink the transistor size, you run into a more complicated problem and your empirical work is useless. If you rely on mechanistic models and simulations, however, they are readily extended to different length scales (if they were properly formulated to begin with, of course).