- Mar 21, 2004
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http://www.anandtech.com/show/4284/sandisktoshiba-take-back-the-crown-with-a-different-kind-of-nand
By definition, wear leveling and ECC has no effect on P/E cycle count. It has an effect on the SSD's lifespan, which is determined by P/E cycles * size / write amplification. Wear leveling algorithms lower the write amplification, thus increasing lifespan on a same P/E cycle count NAND.
The thing is, wear leveling is already very very low... And ECC compensates for lowered reliability (an increase in bit errors during writing, again, due to the lowering quality of NAND as it shrinks; requires sacrificing space to compensate for quality loss).
I don't know why anandtech didn't point out that this is bad spin, but I am concerned about the issue
Like IMFT, they expect to see similar endurance as their 24nm products, around 3,000 program/erase cycles. This is owing to ever improving ECC and wear leveling algorithms, ensuring as few wasted p/e cycles as possible
By definition, wear leveling and ECC has no effect on P/E cycle count. It has an effect on the SSD's lifespan, which is determined by P/E cycles * size / write amplification. Wear leveling algorithms lower the write amplification, thus increasing lifespan on a same P/E cycle count NAND.
The thing is, wear leveling is already very very low... And ECC compensates for lowered reliability (an increase in bit errors during writing, again, due to the lowering quality of NAND as it shrinks; requires sacrificing space to compensate for quality loss).
I don't know why anandtech didn't point out that this is bad spin, but I am concerned about the issue