How are fixed bus speeds possibile and do they cause high latency?

[TerryMathews]

From a CEG standpoint (I've only taken the intro to dig comp hardware course, but it gives a good grasp) how are fixed PCI bus speeds possible? Is this really asynch timing in sheep's clothing which would cause high latency?

I mean, wouldn't the CPU bus have to wait for an edge of the PCI bus to transfer data, which would cause latency equal to the difference between the two bus speeds? Or has there been some sort of revolution that I am unaware of? Maybe some sort of intermediary caching?

 

[Peter]

Well of course it's asynchronous if you're running arbitrary, unconnected frequencies. It's just another "new" marketing buzzword for stuff that's been around for ages. SiS 5571, VIA Apollo VPX ... stuff that dates back deeply into the 1990s.

 

[TerryMathews]

OK then, that's what I thought. Now my next question is why doesn't this cause massive amounts of latency?

 

[Peter]

Mainly because that's a myth anyway.

 

[TerryMathews]

Originally posted by: Peter
Mainly because that's a myth anyway.

I can understand where it comes from though. There must be some sort of buffering going on, otherwise the Athlon would have to wait for the PCI bus's clock to reach an edge, which only occurs 33 times a second. This is slow, considering that the Athlon effectively has a bus that crosses over 266 times a second (My nForce is running at 2x168 or 336).

 

[SuperTool]

Athlon doesn't connect to the PCI bus directly. It connects to the mobo chipset, which in turn connects to the PCI bus. And Athlon doesn't wait for anything. It goes runs some other things and there are interrupts that tell it when something is comming in.
I would tell you to buy a computer book, but why don't you start here and save some cash

 

[Peter]

Originally posted by: TerryMathews

Originally posted by: Peter
Mainly because that's a myth anyway.

I can understand where it comes from though. There must be some sort of buffering going on, otherwise the Athlon would have to wait for the PCI bus's clock to reach an edge, which only occurs 33 times a second. This is slow, considering that the Athlon effectively has a bus that crosses over 266 times a second (My nForce is running at 2x168 or 336).

It doesn't work that way. CPU, AGP, peripheral system bus, and the memory controller are all agents on a north bridge internal "bus". There are deep buffers in all directions, transfer completion not being waited for anyway.

The transfer latencies are in how efficient the chipset north bridge is, not so much in what frequencies those busses run at. Sure, it's more difficult when the bus clocks aren't the same, but it can be done well.

 

[TerryMathews]

Originally posted by: SuperTool
I would tell you to buy a computer book, but why don't you start here and save some cash

I'll hold off on buying a book; I'll get into those CEG courses next year sometime. Just took my intro course.