Holy Crapola: Motorola completes 1.6GHz PowerPC G5. 64 and 32 bit capable

[AGodspeed]

Here's the link. And here's a little bit of what they say:

Beyond far higher clock speeds, the G5 will be a full 64-bit chip, but will support 32-bit addressing at full speed. The part will also support multi-processor configurations.

The G5 will sport a 400MHz frontside bus - like Intel's Pentium 4, though its performance could be limited by whatever memory technology Apple connects to it across the system bus.

Old news but good news.

 

[fkloster]

Good God. That sucker is gonna smoke everthing!!! (...in photoshop that is )

 

[GTaudiophile]

Hmmm...wonder if Apple will get in bed with RAMBUS?

 

[Windogg]

Apple + Rambust = Fruity RIMMjob?

/me shudders.

Windogg

 

[MichaelD]

ROFLMFAO @ Windogg!!! Bwahahahahahahaha! That's the damn funniest thing I've read all week! Good stuff. Fruity Rimmjob!
me\<----must change drawers because I laughed too hard and had an accident!

 

[Athlon4all]

ROFL! Good one Windogg! ROFL!

 

[PliotronX]

<< Apple + Rambust = Fruity RIMMjob? >>


ROFLMAOPIMP

 

[nortexoid]

they should couple it w/ 72-pin EDO memory....

bring it back!....
(sing it back)

 

[ST4RCUTTER]

It's got a fast bus for sure, like the P4. Anybody know the details on this proc? Like its FSB bandwidth? That would really determine how well it would mate with RDRAM...

 

[smp]

I'm looking forward to it

 

[fkloster]

Motorola 1.6 ghz 64bit speedster w/OSX? Hmmmm I love motorola. I wish they made parts for PC's as well

 

[AGodspeed]

Anybody know the details on this proc? Like its FSB bandwidth? That would really determine how well it would mate with RDRAM...

1. Pipeline increased to 10 stages from 7 (enables higher MHz).
2. Transistor count = 58 million.
3. SOI (silicon on insulator) technology.
4. Possibly HyperTransport for chip-to-chip communications.

Umm...HyperTransport, SOI, 64 bit + full speed 32 bit support, increased pipeline...This is sounding a lot like our friend Mr. Hammer.

 

[Sohcan]

Very very cool...I just hope Motorola can stay afloat long enough to release it. :Q

Unfortunatly, I can see Apple's marketing spin already...."Our competition's CPUs are 32-bit, but we have the 64-bit G5! Therefore the G5 must be twice as fast!"....sigh....

 

[AGodspeed]

bump cus everyone should know about this

 

[Dragoon42]

hrm...hope i don't sound too stupid but whats the difference between 32 and 64 bit? i mean i know 64 is higher and stuff but what will it allow it to do?

 

[zephyrprime]

<< hrm...hope i don't sound too stupid but whats the difference between 32 and 64 bit? i mean i know 64 is higher and stuff but what will it allow it to do? >>



Big question but I will give way oversimplified and terse answer.

1. Can do 64bit arithmatic in one instuction rather having to do it as two 32bit parts, carrying the one, and stitching the results together.

2. Can address 2^64 bytes of memory rather 2^32 bytes of memory. Specifically, 32bit machines can only have 4gigs of memory which is too little for many databases and big scientific apps nowadays. 64bit machines can theoretically have 18446744073709551616 bytes of memory.

 

[RanDum72]

Maybe it has a quad-pumped bus using DDR instead of Rambust (kinda like an nForce) .

 

[Sunner]

The real question is, will they be available soon enough?
If they don't show up until 2003 a 1.6 GHz'er won't be all that much good even if it manages to maintain the IPC of the G4.

And considdering Apple's execution ability... lets just say I wont hold my breath.

 

[Sohcan]

<< 1. Can do 64bit arithmatic in one instuction rather having to do it as two 32bit parts, carrying the one, and stitching the results together. >>

But don't let this fool you into thinking that a 64-bit CPU will somehow be twice as fast as a 32-bit CPU. Most arithmetic is handled using SISD instructions (Single Instruction, Single Data), ie, 2 operands and one result. If you're doing 1 + 1, it doesn't matter in terms of performance if you express the operands as a 64-bit integer and do the arithmetic on a 64-bit CPU, or express them as a 32-bit integer and execute the arithmetic on a 32-bit CPU; both operations will be carried out at the same speed (actually, the 64-bit add may have a slightly higher latency, depending on the type of carry-lookahead adder used). A vast majority of the time, 32-bit code for a 32-bit CPU only needs 32-bit integers, so there is no performance advantage of the 64-bit CPU's ability to do 64-bit SISD instructions. Floating-point arithmetic does benefit from increased accuracy from increased bit-width, but x87 already does 80-bit internal precision for FP math.

SIMD instructions, on the other hand, do benefit from wider adders. For example, a 64-bit SIMD unit could do 2 32-bit adds at once, and a 128-bit SIMD unit could do 4 32-bit adds at once. But both the G4 and P4/Athlon already have 128-bit SIMD with Altivec and SSE.

In fact, all else being equal, a 64-bit CPU (especially one with fixed-length instructions like PowerPC) will be 5-10% slower than its 32-bit counterpart. Since the instructions and data are twice as large, the L1 and L2 caches will be able to store fewer instructions and data, resulting in lower hit rates. The speed disadvantage can be overcome by including larger caches.