High K gate metal candidates

[verndewd]

So far I know of Ni/TiN/W as mention in passing in some articles.I read about Hf for the dielectric insulator,which is oxidized.Hf is some crazy cool stuff.But I am wondering about the gate metals themselves now and the Til and upper cap layers,where applicable to explain Possible Intel AMD choices for metals/materials.

 

[Varmint]

Aluminum is also a candidate for gate material. Honestly I don't think it matters that much - the reason they have to use metal is cause it allows them to use a high k gate oxide - poly silicon doesn't work well.

 

[verndewd]

The poly silicon only works to a point ,after a certain amont of scaling it leaks current into the substrate.Hfo2 is the new dielectric insulator that replaces it.

The gates however are quite a different story.Aluminum doesnt have the properties to make a gate scream,so to speak.for that we need to consider other materials.And those metals possibly enhanced with a super conductive metal as well.

 

[verndewd]

in reading the literature, it appears intel may be using ruthenium and tantalum for the metal gates. it seems ibm/amd are moving in a different direction, using full silicidation (fusi). does anyone have any info in this regard? thanks,

learning man

learning man tuned me into this,for which i am greatful.i misread BE as beryllium on Ibm pdf.so as far as gates are concerned,its still a mystery metal.

http://regmedia.co.uk/2007/01/28/ibmhighk.pdf

http://periodic.lanl.gov/elements/4.html

Dielectric Deposition is a process used to deposit a thin layer of insulating material onto the wafer using
Chemical Vapor Deposition (CVD) technology. Two dielectrics commonly used in semiconductor processing are silicon dioxide and silicon nitride. Advanced dielectrics include low dielectric constant (low k) films for copper interconnects, strain-inducing films to boost device performance, and patterning films and gap fill films to enable geometric scaling.

http://www.appliedmaterials.com/products/dielectric_dep_4.html

http://www.pennwellblogs.com/sst/eds_th...27-applied-hkmg-ready-when-you-are.php

and tantalum alloys for the NMOS MG. Expect to see the PMOS electrode material?likely either a titanium or tungsten alloy?emerge within the next 6 months.

theres my answer.Ti/Ta/W/Ru would be a cool addition as far as i can understand.What interests me now is the CVD process and how one would control the deposition and equalization of whatever enhanced metals that are used.Obviously temperature plays a huge role in this,and i find it fascinating to think of molecular deposition via chemical and heat and how you would equalize the distribution of enhancements to the metal,say if you used Ru with W or Ta/Ti and what nitidization does to Ti.

I get a visualization from SiGe and how stressing it would enhance its capabilities,that is some cool stuff,just looking for that picture in my mind on the gates.

🙂 more goodies http://sst.pennnet.com/display_article/...-45nm-chip-with-high--k-,-metal-gates/

 

[Varmint]

Originally posted by: verndewd
theres my answer.Ti/Ta/W/Ru would be a cool addition as far as i can understand.What interests me now is the CVD process and how one would control the deposition and equalization of whatever enhanced metals that are used.Obviously temperature plays a huge role in this,and i find it fascinating to think of molecular deposition via chemical and heat and how you would equalize the distribution of enhancements to the metal,say if you used Ru with W or Ta/Ti and what nitidization does to Ti.
[/L]

Well, CVD is used for Tungsten or Al, but not for Ti or Ta, PVD is usually used for those (a physical sputtering process). You can only use a gas plasma if the metal is volatile (Al yes, Cu no). There is also electroplating - which is used for the copper interconnects. And yeah, temperature is very important, because it limits when you can put down a layer. Whatever temperature process you use, can't be close to the melting point of any material you've already put down on the wafer. Can't use high temperatures (over 200C) with photoresist masks either.

A newer process is ALD (atomic layer deposition) - it's a kind of CVD, and is used to put down the 12 angstrom gate oxide layer. Can also be used for Ru deposition - but that's very new.

I don't know much about metals, I'm an oxide etch guy.

 

[Varmint]

Originally posted by: verndewd
The poly silicon only works to a point ,after a certain amont of scaling it leaks current into the substrate.Hfo2 is the new dielectric insulator that replaces it.

The gates however are quite a different story.Aluminum doesnt have the properties to make a gate scream,so to speak.for that we need to consider other materials.And those metals possibly enhanced with a super conductive metal as well.

Well, since it's the 'highly technical' forum . . . 🙂

HfO2 doesn't replace poly silicon (the gate material), it replaces silicon dioxide (gate oxide), which is lower k value (better insulator). By using a higher k value (worse insulator), they can make a thicker insulator which will mean tunneling electrons have travel further to leak through.

They probably mean IBM will use Fusi at 65 nm, not 45. Fusi uses Nickel Siliciding = they dope the gates with Ni to lower resistance. I think they're going to need metal gates, Fusi is not good enough. Ni siliciding also loses its characteristics above 400C, so it limits what processes you can use afterwards. IBM didn't use this at 90 nm for that reason. Maybe they'll use W or Cobalt, dunno, but metal gates are probably required at 45 nm.

While it's true that Al is not ideal - they have to be limited by what's manufacturable. Gate length is critical to speed - right now they use resist trimming to etch such a tiny gate. Can they get the same tiny ~35-40 nm length (for 65 nm node) as precisely when etching metal? I'm not sure, it's either impossible or difficult, depending on the metal. But I dunno, it's not my area. 🙂 Anyway, I'm saying there are many process limitations, they have to choose the metal alloys carefully.

 

[BrownTown]

Originally posted by: Varmint
Well, since it's the 'highly technical' forum . . . 🙂

HfO2 doesn't replace poly silicon (the gate material), it replaces silicon dioxide (gate oxide), which is lower k value (better insulator). By using a higher k value (worse insulator), they can make a thicker insulator which will mean tunneling electrons have travel further to leak through.

Higher k values are not worse insulators (thats just silly). High-k dielectrics are used because capacitance is proportional to the relative permitivity (Er or k) of the dielectric. Capacitance is also inversely proportional to the distance between the two "plates" in the capacitor. Using a higher k dielectric allows you to have a thicker gate oxide and still have the same capacitance. Since the current 1.2 nm SiO2 gate oxides are only ~5 atoms thick they leak a good deal to electron tunneling. A 3nm gate of a material like say HfSiON could have a greater capacitance and at the same time have a much lower leakage current. This would result in a higher drive current (faster transistors), and a lower leakage (more power efficient transistors).

EDIT: on another note low-k dielectrics are also all the rage in processors too. You might hear a company bragging about having high-k dielectrics and low-k dielectrics in the same chip and get confused. This is because in the gate oxide a high-k value is very usefull because capacitance is a good quality. However in the insualtors between the metal layers parasitic capacitance plays a huge factor in increasing drive times across a circuit and therefore slowing down a chip. So using low-k between metal layers is very usefull.

 

[Varmint]

Originally posted by: BrownTown

Originally posted by: Varmint
Well, since it's the 'highly technical' forum . . . 🙂

HfO2 doesn't replace poly silicon (the gate material), it replaces silicon dioxide (gate oxide), which is lower k value (better insulator). By using a higher k value (worse insulator), they can make a thicker insulator which will mean tunneling electrons have travel further to leak through.

Higher k values are not worse insulators (thats just silly). High-k dielectrics are used because capacitance is proportional to the relative permitivity (Er or k) of the dielectric. Capacitance is also inversely proportional to the distance between the two "plates" in the capacitor. Using a higher k dielectric allows you to have a thicker gate oxide and still have the same capacitance. Since the current 1.2 nm SiO2 gate oxides are only ~5 atoms thick they leak a good deal to electron tunneling. A 3nm gate of a material like say HfSiON could have a greater capacitance and at the same time have a much lower leakage current. This would result in a higher drive current (faster transistors), and a lower leakage (more power efficient transistors).

EDIT: on another note low-k dielectrics are also all the rage in processors too. You might hear a company bragging about having high-k dielectrics and low-k dielectrics in the same chip and get confused. This is because in the gate oxide a high-k value is very usefull because capacitance is a good quality. However in the insualtors between the metal layers parasitic capacitance plays a huge factor in increasing drive times across a circuit and therefore slowing down a chip. So using low-k between metal layers is very usefull.

You are saying the same thing, but I'm not sure you know it.

I'm not interested in getting into a google war with you. Nor do I need a lecture on basic physics, i can google that myself if I forget stuff.

A gate is not designed to be a capacitor - if so, they would have used high k dielectrics a long time ago. Why didn't they?

Because the goal of the gate design is not to be a good capacitor, it's simply to be good enough that it attracts the electrons in the silicon channel enough to let current flow from source to drain. As the turn on voltages keep dropping, it gets harder and harder to attract those electrons. So they move the gate closer to the channel, or use high k insulators.

If they wanted better capacitance, they'd simply use a longer gate.

And I know what low-k films are, I etch them at work.

 

[BrownTown]

No, its really not saying the same thing. Its true of course the purpose of the gate is not to be a capacitor in its own right (in fact a higher capacitance in the gate leads to higher dynamic power losses). However, the gate oxide does act very much like the gap in a capacitor between the gate and the channel. To be more accurate as for why a high-k dielectric would be preferable you can consider that the electric dispalcement vector is proportional to the electric field via the relative permitivity of the gate dielectric. This means that a high-k dielectric will have a small electric displacement vector opposing the flow of charge onto the gate electrode. This results in a large buildup of charge on the gate. In a capacitor this is a good thing because it means you build up more energy storage. In a transistor this is a good thing because it means that there are more charges on the gate to drive away charges in the channel. This means that channel inversion happens more rapidly and more completely. As stated before this results in faster switching and higher drive currents. The statement about simply increasing the area of the gate (I assume thats what you mean be longer) doesn't work because the shrinking of the feature size which is the driving force in the semiconductor processes will invariably result in smaller and smaller gate areas. As for why high-k dielectrics were not used before, it is simply because high-k dielectrics present a considerable problem in that the materials used (HfO2 HfSiON etc...) do not bond well with polysilicon in the same way that SiO2 does. Therefore metal gates must be used instead of polysilicon which of course leads to many new problems of how to incoorperate these new materials into the current process flow. In the past they simply made thinner and thinner gate oxides which has the same effect as high-k, but uses the same materials that are very well understood. However the current 1.2nm gate oxide simply cannot get any smaller and therefore process engineers are forced to turn to high-k dielectrics in order to obtain the scaling called for by Moore's Law.

If I missed something here please tell me, I am simply going on memmory, so it is possible that the wrong term was used somewhere (like permitivity vs permeability, i always get those messed up). However I beleive the overall idea is correct. It is possible that the explanations used in the field verse those used in a classroom setting (the basis of my knowledge) are different, but I am pretty sure what I am saying is correct so far as I have been taught on the subject (which is not a trivial amount, though of course I am no expert either).

EDIT: spelling

 

[Varmint]

Originally posted by: BrownTown
No, its really not saying the same thing. Its true of course the purpose of the gate is not to be a capacitor in its own right (in fact a higher capacitance in the gate leads to higher dynamic power losses). However, the gate oxide does act very much like the gap in a capacitor between the gate and the channel. To be more accurate as for why a high-k dielectric would be preferable you can consider that the electric dispalcement vector is proportional to the electric field via the relative permitivity of the gate dielectric. This means that a high-k dielectric will have a small electric displacement vector opposing the flow of charge onto the gate electrode. This results in a large buildup of charge on the gate. In a capacitor this is a good thing because it means you build up more energy storage. In a transistor this is a good thing because it means that there are more charges on the gate to drive away charges in the channel. This means that channel inversion happens more rapidly and more completely. As stated before this results in faster switching and higher drive currents. The statement about simply increasing the area of the gate (I assume thats what you mean be longer) doesn't work because the shrinking of the feature size which is the driving force in the semiconductor processes will invariably result in smaller and smaller gate areas. As for why high-k dielectrics were not used before, it is simply because high-k dielectrics present a considerable problem in that the materials used (HfO2 HfSiON etc...) do not bond well with polysilicon in the same way that SiO2 does. Therefore metal gates must be used instead of polysilicon which of course leads to many new problems of how to incoorperate these new materials into the current process flow. In the past they simply made thinner and thinner gate oxides which has the same effect as high-k, but uses the same materials that are very well understood. However the current 1.2nm gate oxide simply cannot get any smaller and therefore process engineers are forced to turn to high-k dielectrics in order to obtain the scaling called for by Moore's Law.

If I missed something here please tell me, I am simply going on memmory, so it is possible that the wrong term was used somewhere (like permitivity vs permeability, i always get those messed up). However I beleive the overall idea is correct. It is possible that the explanations used in the field verse those used in a classroom setting (the basis of my knowledge) are different, but I am pretty sure what I am saying is correct so far as I have been taught on the subject (which is not a trivial amount, though of course I am no expert either).

EDIT: spelling

You learned this in a classroom? Which classes were these?

I just noticed there's 3 of us discussing this actually, lol. I thought I was replying to the original poster.

 

[Varmint]

Originally posted by: BrownTown
No, its really not saying the same thing. Its true of course the purpose of the gate is not to be a capacitor in its own right (in fact a higher capacitance in the gate leads to higher dynamic power losses). However, the gate oxide does act very much like the gap in a capacitor between the gate and the channel. To be more accurate as for why a high-k dielectric would be preferable you can consider that the electric dispalcement vector is proportional to the electric field via the relative permitivity of the gate dielectric. This means that a high-k dielectric will have a small electric displacement vector opposing the flow of charge onto the gate electrode. This results in a large buildup of charge on the gate. In a capacitor this is a good thing because it means you build up more energy storage. In a transistor this is a good thing because it means that there are more charges on the gate to drive away charges in the channel. This means that channel inversion happens more rapidly and more completely. As stated before this results in faster switching and higher drive currents. The statement about simply increasing the area of the gate (I assume thats what you mean be longer) doesn't work because the shrinking of the feature size which is the driving force in the semiconductor processes will invariably result in smaller and smaller gate areas. As for why high-k dielectrics were not used before, it is simply because high-k dielectrics present a considerable problem in that the materials used (HfO2 HfSiON etc...) do not bond well with polysilicon in the same way that SiO2 does. Therefore metal gates must be used instead of polysilicon which of course leads to many new problems of how to incoorperate these new materials into the current process flow. In the past they simply made thinner and thinner gate oxides which has the same effect as high-k, but uses the same materials that are very well understood. However the current 1.2nm gate oxide simply cannot get any smaller and therefore process engineers are forced to turn to high-k dielectrics in order to obtain the scaling called for by Moore's Law.

If I missed something here please tell me, I am simply going on memmory, so it is possible that the wrong term was used somewhere (like permitivity vs permeability, i always get those messed up). However I beleive the overall idea is correct. It is possible that the explanations used in the field verse those used in a classroom setting (the basis of my knowledge) are different, but I am pretty sure what I am saying is correct so far as I have been taught on the subject (which is not a trivial amount, though of course I am no expert either).

EDIT: spelling

Reading your two posts, you're correct in what you're saying, but I think you shouldn't focus on capacitance when thinking about a gate. What makes an IC switch faster is not a high capacitance gate, it's making the channel shorter, while at the same time reducing turn-on voltage. This is why you need thinner gate oxides. It's a cart before the horse thing - you need shorter gate length, therefore you need more capacitance in the gate/channel interface. But gate capacitance by itself isn't a benefit. Maybe you got the distinction already, if so never mind.

As I said, you could increase capacitance on a gate by making it wider - the width of the gate doesn't affect speed, only the length. But increasing gate capacitance in this way won't gain you any real speed (the wells are not any closer together), so they don't do it.

HfO2 bonds fine with poly silicon, it's not really the issue (there are many). IBM is working on high k HfO2 with poly silicon gates.

 

[Special K]

Originally posted by: Varmint

Originally posted by: BrownTown
No, its really not saying the same thing. Its true of course the purpose of the gate is not to be a capacitor in its own right (in fact a higher capacitance in the gate leads to higher dynamic power losses). However, the gate oxide does act very much like the gap in a capacitor between the gate and the channel. To be more accurate as for why a high-k dielectric would be preferable you can consider that the electric dispalcement vector is proportional to the electric field via the relative permitivity of the gate dielectric. This means that a high-k dielectric will have a small electric displacement vector opposing the flow of charge onto the gate electrode. This results in a large buildup of charge on the gate. In a capacitor this is a good thing because it means you build up more energy storage. In a transistor this is a good thing because it means that there are more charges on the gate to drive away charges in the channel. This means that channel inversion happens more rapidly and more completely. As stated before this results in faster switching and higher drive currents. The statement about simply increasing the area of the gate (I assume thats what you mean be longer) doesn't work because the shrinking of the feature size which is the driving force in the semiconductor processes will invariably result in smaller and smaller gate areas. As for why high-k dielectrics were not used before, it is simply because high-k dielectrics present a considerable problem in that the materials used (HfO2 HfSiON etc...) do not bond well with polysilicon in the same way that SiO2 does. Therefore metal gates must be used instead of polysilicon which of course leads to many new problems of how to incoorperate these new materials into the current process flow. In the past they simply made thinner and thinner gate oxides which has the same effect as high-k, but uses the same materials that are very well understood. However the current 1.2nm gate oxide simply cannot get any smaller and therefore process engineers are forced to turn to high-k dielectrics in order to obtain the scaling called for by Moore's Law.

If I missed something here please tell me, I am simply going on memmory, so it is possible that the wrong term was used somewhere (like permitivity vs permeability, i always get those messed up). However I beleive the overall idea is correct. It is possible that the explanations used in the field verse those used in a classroom setting (the basis of my knowledge) are different, but I am pretty sure what I am saying is correct so far as I have been taught on the subject (which is not a trivial amount, though of course I am no expert either).

EDIT: spelling

Reading your two posts, you're correct in what you're saying, but I think you shouldn't focus on capacitance when thinking about a gate. What makes an IC switch faster is not a high capacitance gate, it's making the channel shorter, while at the same time reducing turn-on voltage. This is why you need thinner gate oxides. It's a cart before the horse thing - you need shorter gate length, therefore you need more capacitance in the gate/channel interface. But gate capacitance by itself isn't a benefit. Maybe you got the distinction already, if so never mind.

As I said, you could increase capacitance on a gate by making it wider - the width of the gate doesn't affect speed, only the length. But increasing gate capacitance in this way won't gain you any real speed (the wells are not any closer together), so they don't do it.

HfO2 bonds fine with poly silicon, it's not really the issue (there are many). IBM is working on high k HfO2 with poly silicon gates.

Maybe I'm misunderstanding what you are saying, but how can you say that increasing the gate capacitance does not make ICs switch faster? The drain current of a MOSFET is directly proportional to the capacitance of the gate oxide. It is also inversely proportional to L, as you also indicated.

You also said the width of the gate doesn't increase speed, but the drain current is also proportional to the width of the transistor. Typically the lengths of the devices are made minimum size, but if the drive strength of a particular transistor needs to be increased by the circuit designer, it is done by increasing the width of the device.

 

[Varmint]

Maybe I'm misunderstanding what you are saying, but how can you say that increasing the gate capacitance does not make ICs switch faster? The drain current of a MOSFET is directly proportional to the capacitance of the gate oxide. It is also inversely proportional to L, as you also indicated.

You also said the width of the gate doesn't increase speed, but the drain current is also proportional to the width of the transistor. Typically the lengths of the devices are made minimum size, but if the drive strength of a particular transistor needs to be increased by the circuit designer, it is done by increasing the width of the device.

It's gate capacitance (per unit area) that affects drain current. And you would also benefit from a wider gate because resistance would be lower.

I think you shouldn't obsess with the equations and forget you're making a chip - there are millions of FETs, so you only make the changes that will benefit you overall, and ones that are manufacturable. A wider gate would make your CPU bigger, slower and hotter overall, even though drain current would be higher.

You said Hf gate oxides give you higher drive current so the chip is faster. That's only true if you make the gate length smaller at the same time, it's not true by itself. That's my point.

 

[Varmint]

 

[Varmint]

Let's drop the google equation war, and get back on the topic, which is metal gate materials.

 

[Special K]

Originally posted by: Varmint

Maybe I'm misunderstanding what you are saying, but how can you say that increasing the gate capacitance does not make ICs switch faster? The drain current of a MOSFET is directly proportional to the capacitance of the gate oxide. It is also inversely proportional to L, as you also indicated.

You also said the width of the gate doesn't increase speed, but the drain current is also proportional to the width of the transistor. Typically the lengths of the devices are made minimum size, but if the drive strength of a particular transistor needs to be increased by the circuit designer, it is done by increasing the width of the device.

It's gate capacitance (per unit area) that affects drain current. And you would also benefit from a wider gate because resistance would be lower.

I think you shouldn't obsess with the equations and forget you're making a chip - there are millions of FETs, so you only make the changes that will benefit you overall, and ones that are manufacturable. A wider gate would make your CPU bigger, slower and hotter overall, even though drain current would be higher.

You said Hf gate oxides give you higher drive current so the chip is faster. That's only true if you make the gate length smaller at the same time, it's not true by itself. That's my point.

You are correct that a wider gate would increase power consumption due to the increased drain current, but are you trying to say that all transistors on a chip are minimum sized? That is not correct. Take an inverter for instance. If you want to have equal tphl and tplh, you would typically make the PMOS devices twice as wide as the NMOS device to offset the lower mobility of holes compared to electrons.

 

[verndewd]

AWESOME this is more info than i have gotten in months at other sites forums 😉

 

[verndewd]

Originally posted by: Varmint

Originally posted by: BrownTown
No, its really not saying the same thing. Its true of course the purpose of the gate is not to be a capacitor in its own right (in fact a higher capacitance in the gate leads to higher dynamic power losses). However, the gate oxide does act very much like the gap in a capacitor between the gate and the channel. To be more accurate as for why a high-k dielectric would be preferable you can consider that the electric dispalcement vector is proportional to the electric field via the relative permitivity of the gate dielectric. This means that a high-k dielectric will have a small electric displacement vector opposing the flow of charge onto the gate electrode. This results in a large buildup of charge on the gate. In a capacitor this is a good thing because it means you build up more energy storage. In a transistor this is a good thing because it means that there are more charges on the gate to drive away charges in the channel. This means that channel inversion happens more rapidly and more completely. As stated before this results in faster switching and higher drive currents. The statement about simply increasing the area of the gate (I assume thats what you mean be longer) doesn't work because the shrinking of the feature size which is the driving force in the semiconductor processes will invariably result in smaller and smaller gate areas. As for why high-k dielectrics were not used before, it is simply because high-k dielectrics present a considerable problem in that the materials used (HfO2 HfSiON etc...) do not bond well with polysilicon in the same way that SiO2 does. Therefore metal gates must be used instead of polysilicon which of course leads to many new problems of how to incoorperate these new materials into the current process flow. In the past they simply made thinner and thinner gate oxides which has the same effect as high-k, but uses the same materials that are very well understood. However the current 1.2nm gate oxide simply cannot get any smaller and therefore process engineers are forced to turn to high-k dielectrics in order to obtain the scaling called for by Moore's Law.

If I missed something here please tell me, I am simply going on memmory, so it is possible that the wrong term was used somewhere (like permitivity vs permeability, i always get those messed up). However I beleive the overall idea is correct. It is possible that the explanations used in the field verse those used in a classroom setting (the basis of my knowledge) are different, but I am pretty sure what I am saying is correct so far as I have been taught on the subject (which is not a trivial amount, though of course I am no expert either).

EDIT: spelling

Reading your two posts, you're correct in what you're saying, but I think you shouldn't focus on capacitance when thinking about a gate. What makes an IC switch faster is not a high capacitance gate, it's making the channel shorter, while at the same time reducing turn-on voltage. This is why you need thinner gate oxides. It's a cart before the horse thing - you need shorter gate length, therefore you need more capacitance in the gate/channel interface. But gate capacitance by itself isn't a benefit. Maybe you got the distinction already, if so never mind.

As I said, you could increase capacitance on a gate by making it wider - the width of the gate doesn't affect speed, only the length. But increasing gate capacitance in this way won't gain you any real speed (the wells are not any closer together), so they don't do it.

HfO2 bonds fine with poly silicon, it's not really the issue (there are many). IBM is working on high k HfO2 with poly silicon gates.

I read that intel couldnt get it to bond and thats why the used a metal gate,,,,let me retrace,,,,,,,intel wanted Hfo2 and couldnt use traditional gate materials because of bonding issues.does that sound right?I am going on a week old memory.

 

[ramuman]

Not sure its been covered here yet, but metal gates also have a big advantage in tuning the phi(ms) (the metal-semiconductor workfunction difference). With Si, in the best case, you're looking at Ec-Ev ~ 1.1eV. Not sure how much Intel needed this benefit, but I'm almost certain it mattered.

 

[Special K]

Originally posted by: ramuman
Not sure its been covered here yet, but metal gates also have a big advantage in tuning the phi(ms) (the metal-semiconductor workfunction difference). With Si, in the best case, you're looking at Ec-Ev ~ 1.1eV. Not sure how much Intel needed this benefit, but I'm almost certain it mattered.

Does that really make a big difference in the work function? Poly-Si gates are typically doped so highly that they are practically metals anyway. The Fermi level is almost even with the conduction band.

 

[ramuman]

Originally posted by: Special K

Originally posted by: ramuman
Not sure its been covered here yet, but metal gates also have a big advantage in tuning the phi(ms) (the metal-semiconductor workfunction difference). With Si, in the best case, you're looking at Ec-Ev ~ 1.1eV. Not sure how much Intel needed this benefit, but I'm almost certain it mattered.

Does that really make a big difference in the work function? Poly-Si gates are typically doped so highly that they are practically metals anyway. The Fermi level is almost even with the conduction band.

You can have a much larger range of metal work functions though. Like I said though, not sure how much that alone was a factor. Metal gates have other advantages over Poly-Si (e.g. less gate depletion).

A couple of years ago, I think the end result was that industry settled on fully silicided metals for the gate (I've seen some of Intel's IEDM papers where NiSi was the weapon of choice in this manner).

Intel didn't detail too much about the 45nm node, so I'm unsure, and they're right to protect their IP. They're basically going to be the first to implement a full high-k process in mass production, so what ever they're doing must be working.

 

[cougar1]

@verndewd - Regarding PolySi/HfO2

The issue isn't that PolySi can't bond to HfO2, but that the highly-reducing silane ambient used to deposit PolySi causes reduction of the HfO2 surface, leading to the formation of Hf silicide (or at least Hf-Si bonding). These Hf-Si bonds result in electronic states that pin the fermi level near midgap, so it becomes impossible to tune the gate workfunction as needed to get low-threshold-voltage devices (see [1] for more details).

Workarounds are probably possible using alternate deposition processes (eg. sputtering or alternate CVD chemistries). However, development of such novel processes would require similar levels of investment as development of metal gates and the poly gates would still suffer from depletion effects, so most companies decided to abandon poly gates and focus on metal gates.

[1] J. K. Schaeffer et al., Appl. Phys. Lett., 85, pg. 1826, 2004


@ramuman - Regarding metal work functions

For optimal performance, you need gates with workfunctions near the conduction band edge for nmos (eg ~3.9 eV) and near the valence band edge for pmos (eg. ~5.0 eV). For Poly/SiO2, you could get pretty close by heavily doping the Poly to either P-type or N-type. In fact the ability to tune the Poly effective work function to either band edge simply by using the appropriate dopant (n- or p-type) was a major advantage. However as mentioned above, for Poly/HfO2 fermi level pinning becomes a problem and the fermi level is constrained near midgap (eg. 4.4 eV) regardless of doping. Plus, you have the depletion effects you mentioned.

While you are right that a metal gate provides access to a wider range of workfunctions, the problem becomes one of finding metals that are both compatible with conventional process technology (eg. high temperature anneals) and have the appropriate workfunctions (~3.9eV for nmos and ~5.0eV for pmos). This is especially difficult because for a metal it is very difficult to "tune" the work function through doping or other means.

From what I've seen in the literature, TaC (or TaCN), seems to do a fairly good job for nmos, but people have struggled to find a good metal gate for pmos. Candidates I have seen used are Pt, OsO2, RuO2, MoO2, MoN, and ReO2. But all of these have issues in terms of compatibility with conventional processing. So it is possible that the recent announcements have more to do with changes to the processing (eg. replacement gates) than to the use of novel materials.

FUSI gates are another possibility for both nmos and pmos, but these have their own set of problems.

 

[verndewd]

Originally posted by: cougar1
@verndewd - Regarding PolySi/HfO2

The issue isn't that PolySi can't bond to HfO2, but that the highly-reducing silane ambient used to deposit PolySi causes reduction of the HfO2 surface, leading to the formation of Hf silicide (or at least Hf-Si bonding). These Hf-Si bonds result in electronic states that pin the fermi level near midgap, so it becomes impossible to tune the gate workfunction as needed to get low-threshold-voltage devices (see [1] for more details).

Workarounds are probably possible using alternate deposition processes (eg. sputtering or alternate CVD chemistries). However, development of such novel processes would require similar levels of investment as development of metal gates and the poly gates would still suffer from depletion effects, so most companies decided to abandon poly gates and focus on metal gates.

[1] J. K. Schaeffer et al., Appl. Phys. Lett., 85, pg. 1826, 2004


@ramuman - Regarding metal work functions

For optimal performance, you need gates with workfunctions near the conduction band edge for nmos (eg ~3.9 eV) and near the valence band edge for pmos (eg. ~5.0 eV). For Poly/SiO2, you could get pretty close by heavily doping the Poly to either P-type or N-type. In fact the ability to tune the Poly effective work function to either band edge simply by using the appropriate dopant (n- or p-type) was a major advantage. However as mentioned above, for Poly/HfO2 fermi level pinning becomes a problem and the fermi level is constrained near midgap (eg. 4.4 eV) regardless of doping. Plus, you have the depletion effects you mentioned.

While you are right that a metal gate provides access to a wider range of workfunctions, the problem becomes one of finding metals that are both compatible with conventional process technology (eg. high temperature anneals) and have the appropriate workfunctions (~3.9eV for nmos and ~5.0eV for pmos). This is especially difficult because for a metal it is very difficult to "tune" the work function through doping or other means.

From what I've seen in the literature, TaC (or TaCN), seems to do a fairly good job for nmos, but people have struggled to find a good metal gate for pmos. Candidates I have seen used are Pt, OsO2, RuO2, MoO2, MoN, and ReO2. But all of these have issues in terms of compatibility with conventional processing. So it is possible that the recent announcements have more to do with changes to the processing (eg. replacement gates) than to the use of novel materials.

FUSI gates are another possibility for both nmos and pmos, but these have their own set of problems.

coolio.so its the process itself that makes it problematic.I dont get answers like this in other forums.Glad i joined.Now i will go and research all the metals you mentioned.
The more info the merrier.

I have no clue why I am so interested in this,I just think its fascinating;I am a musician ,man,,,,,while its not all that i can do It doesnt explain my passion for cpu knowledge.Maybe its a passing thing 🙂

 

[verndewd]

Pt, OsO2, RuO2, MoO2, MoN, and ReO2

platinum,osmium oxide,ruthenium oxide,molybdenum nitride,Rhenium oxide.
exotic metals.several platinoids.crazy i can see why the choice for these.

http://periodic.lanl.gov/default.htm

 

[cougar1]

Originally posted by: verndewd
Pt, OsO2, RuO2, MoO2, MoN, and ReO2

platinum,osmium oxide,ruthenium oxide,molybdenum nitride,Rhenium oxide.
exotic metals.several platinoids.crazy i can see why the choice for these.

http://periodic.lanl.gov/default.htm

Each of the mentioned metals have relatively high work functions, which is why they are used. The problem is they are not terribly stable and tend to react with the HfO2 and the underlying silicon during subsequent high temperature (eg. 1000C) anneals for dopant diffusion/activation. These reactions, lead to either a lower work function metal or a thick HfO2/SiO2/Si interfacial layer which reduces the effectiveness of the high-k material. Solutions are either to find better materials, less aggressive anneals (eg. laser anneals and spike anneals), or alternate processes where the anneals are performed before depositing the metal. However, each of these approaches has its own challenges and the ultimate solution is likely to be some combination.