to make things clear:
32M x 64 bit denotes the size of the module = 256MB
32M x 72 bit denotes 256MB module with ECC.
32M x 64 bit module could be made by sixteen 16M x 8 bit (4 bank x 4M x 8 bit) SDRAM chips,
or made by eight 32M x 4 bit (4 bank x 8M x 4 bit) chips.
this 32M x4 bit type chip is so-called high density by pricewatch vendors which is not right, the width is just 4 bit while regular is 8 bit, it should be called "narrow width memory".
both are double side, double bank modules.
32M x 64 bit module could also be made by eight 32M x 8 bit (4 bank x 8M x 8bit) chips,
this type of module is single side, single bank module.
this 32M x 8 bit chip is really high density compaing to 16M x 8 bit chip.
according to
ftp://download.intel.com/design/chipsets/datashts/29065602.pdf
810 chipset's integrated DRAM controller
- 8 MB to 256 MB using 16Mb/64Mb technology (512 MB using 128Mb technolgy)
- supports up to 2 double sided DIMM modules
- 64-bit data interface
- 100Mhz system memory bus frequency
- Support for Asymmetrical DRAM addressing only
- Support for x8, x16 and x32 DRAM device width
...
it''s clear that 810 doesn't support x4 width memory - those pricewatch so-called high density chip,
it also doesn't support 256Mb (such as 32M x 8 bit) chip - real high density chip.