Has anyone here ever used VHDL code before?

[CraKaJaX]

I'm having a problem with Altera's Quartus II software. I have all my code written out for a circuit, but when I go to compile it, it gives me "Error: Top-level design entitiy "Project2" is undefined. It tells me to go to general settings and set the top-level design to Project2, but it already is set as that. If it helps any, here is my code:

library ieee;
use ieee.std_logic_1164.all;

entity Project2_VHDL is
port (
A : in std_logic;
B : in std_logic;
C : in std_logic;
D : in std_logic;
Y : out std_logic
);
end Project2_VHDL;



architecture dataflow of Project2_VHDL is

signal wire1: std_logic;
signal wire2: std_logic;
signal wire3: std_logic;
signal wire4: std_logic;
signal wire5: std_logic;
signal wire6: std_logic;

begin

-- Y <= (not C and not D) or (not A and B); This line is commented out

wire1 <= not A;
wire2 <= B;
wire3 <= not C;
wire4 <= not D;
wire5 <= wire1 and wire2;
wire6 <= wire3 and wire4;
Y <= wire5 or wire6;

end dataflow;

Does anyone have ANY idea what is wrong here?

 

[George P Burdell]

The last time I used VHDL was in 2003. Sorry man, don't remember much.

 

[duragezic]

If it is supposed to be "Project2", shouldn't it be

entity Project2 is
...
end Project2;

likewise, change to:

architecture dataflow of Project2 is



Or am I missing something obvious?

 

[mcmilljb]

Yeah, I am having to reach back too. I think I might notice 2 things.

You have:
Y : out std_logic
);
Maybe it should be Y : out std_logic );
because I think you have to have a ; at the end of each line.

Also why do you have _VHDL after each Project2? I could be complaining about that. From there support " Specify the top-level design file name as the project." Maybe it's looking for Project2 but you have Project2_VHDL.

That's just my 2 guesses. Ask the professor on Monday if you don't figure it out.

 

[CraKaJaX]

Holy lord I am stupid. dura, thanks a bunch. It's always the littlest mistake

 

[CraKaJaX]

Another question for you guys:

If the prof is asking "Be sure to vary the inputs A, B, C, D in the binary counting order." How would I go about this? This is my first VHDL project using this software and we haven't gone over much yet. Any help appreciated. Thanks.

 

[mcmilljb]

YHPM

 

[Gerbil333]

Originally posted by: CraKaJaX
Another question for you guys:

If the prof is asking "Be sure to vary the inputs A, B, C, D in the binary counting order." How would I go about this? This is my first VHDL project using this software and we haven't gone over much yet. Any help appreciated. Thanks.

We had a pattern generating app that handled that for us. *shrug*

 

[frostedflakes]

Been a few semesters since I've used Quartus II, and unfortunately I don't have it loaded on my computer now, but I'll try to help. When you go to simulate the circuit and add your inputs, select all the inputs, then right click on them and group them. Then right click on the group and there should be an option in the menu for counting. I don't remember exactly how to define the binary counting order, but you should be able to figure it out. If you can't figure out how to configure a specific thing I could probably help you if you took a few screen shots of the menus that come up. It's just kind of hard to remember everything without the software in front of me.

 

[Casawi]

Originally posted by: duragezic
If it is supposed to be "Project2", shouldn't it be

entity Project2 is
...
end Project2;

likewise, change to:

architecture dataflow of Project2 is



Or am I missing something obvious?

I think he is right.

 

[Casawi]

Originally posted by: CraKaJaX
Another question for you guys:

If the prof is asking "Be sure to vary the inputs A, B, C, D in the binary counting order." How would I go about this? This is my first VHDL project using this software and we haven't gone over much yet. Any help appreciated. Thanks.

? not sure what u mean.

 

[duragezic]

He probably just means

A_B_C_D
0_0_0_0
0_0_0_1
0_0_1_0
0_0_1_1
0_1_0_0
...
1_1_1_0
1_1_1_1


So, 2^4 = 16 possible combinations of input. So just input them in that order, that way you test all possible inputs, and get an output Y for each combination. So put your results like that, in a table, with a column on the right of D for Y (output)

 

[Casawi]

Originally posted by: duragezic
He probably just means

A_B_C_D
0_0_0_0
0_0_0_1
0_0_1_0
0_0_1_1
0_1_0_0
...
1_1_1_0
1_1_1_1


So, 2^4 = 16 possible combinations of input. So just input them in that order, that way you test all possible inputs, and get an output Y for each combination. So put your results like that, in a table, with a column on the right of D for Y (output)

Word. That is what I thought at first, but wasn't sure. I remember doing this shit in Hw/SW integration class.

 

[mcmilljb]

That's essentially a truth table... You could do that without the program unless he wants the waveform table.

 

[frostedflakes]

I'd assume the whole point of the assignment is to familiarize students with the Quartus software, though. Solving logic circuits by hand doesn't further that goal.

 

[duragezic]

Well no, you don't make the program do a truth table, or do it by hand. In Quartus, at whatever point or way you enter input, simply enter the input in that order. You would just use a truth table to present your input and output. It has been a while since I used Quartus so I don't remember how to enter input.

 

[mcmilljb]

Originally posted by: frostedflakes
I'd assume the whole point of the assignment is to familiarize students with the Quartus software, though. Solving logic circuits by hand doesn't further that goal.

That's why you would show the waveform table. It shows the changes in the input and how they affect the output. You need the truth table to compare to make sure it's right.

 

[CraKaJaX]

He emailed me back and replied:

"This is similar to what you have done for project 1. ABCD would vary from 0000 to 1111. A if the MSB and D is the LSB. Use a 10 ms clock for D, 20 ms clock for C, 40 ms for B and 80 ms for D. For end time choose 80 ms.

Hope this helps."

It would of taken me a bit to figure that out. Thank god for professors who sit on their computers and reply to emails on Sunday nights.

 

[Sahakiel]

Personal tip: Become very familiar with reading waveforms. A lot of people look at the code to figure out what's wrong. I prefer looking at the behavior. Much faster.