Hammer - 67 Million transistors - 103 mm^2 die - how?

[YossI]

Here's an interview with Jerry on AMD.


Intresting read.
here's a quote from jerry I can't quite figure out:
"
The Hammer, which is an eighth-generation processor, is 103 square mm, versus our seventh generation, which is 80 square mm. [There are] 67 million transistors in the Hammer?67 million transistors in 130-nanometer technology. It?s extraordinary.
"
Hammers die size is 103mm^2 with 67 million transistors, on 0.13nm process.
how can this be? I know Pentium 4 northwood has 55 million transistors with a die size of 146 mm^2.

Hammer has Higher transistor count and a smaller die size... how can this be?

 

[Sahakiel]

I may be wrong, but I think the reason may be the Northwood core isn't an exact square, so some blank silicon gets factored into die size.

 

[wfbberzerker]

it's the same way with athlon-p4. amd generally packs more into less space

 

[jwo7777777]

Totally different approaches to microprocessor design.

Additionally, you not only have to have transistors on a die, there are interconnects and pads, packaging considerations, testing considerations, thermal issues, emi issues, leakage currents, blah blah blah.........

From design to wafer production to testing to packaging, all these things will impact die size and transistor density.

It is nearly an apples to oranges, even if the ICs perform the same function.

 

[pm]

One part of the answer lies in process technology. One of the benefits of SOI is that well spacing and other key process dimensions can be reduced due to the reduced possibility of "latch-up" - a fatal chip condition that can occur if you put everything too close together on bulk CMOS processes. This allows you put transistors closer together on SOI and thus improve packing density over bulk CMOS processes.

There are also different design methods at different companies. Certain companies put a strong emphasis on minimizing die size (for cost), some put a strong emphasis on reusability (for time to market), some put a strong emphasis on high yield (for cost and predictability), some put a strong emphasis on testability (the ability to minimize the effort and cost associated with testing the chip - which adds space and gates), some put an emphasis on robustness so everything is overengineered (for military apps, for example) and some put an emphasis on flexibility - the ability to easily/quickly reconfigure the chip to adapt to market conditions - and thus add extra logic that is never turned on at all. Nearly everyone designs to a mix of these. I had a different company in mind when I wrote each of the previous statements, but I'd rather not put names to the concepts. But it is true that companies like AMD, IBM, Intel, Motorola, and Texas Instruments all have engineering teams that favor certain things over another. The answer to your question, Yossl, probably lies at least partially in this difference in design methods.

 

[Bozz]

I dont know exactly how a closeup of the cores look like but do they use any multiple layer technology to achieve this? Since it is merely a two dimensional measurement having multiple layers can dramatically cut down the surface area...

 

[YossI]

Thanx For all the answers.

always thought that the number of transistors has liner relation to die size...
well... I better dig up some more on CPU design and stuff

 

[Eskimo]

Saw an interesting presentation by AMD yesterday. In it they were talking about their future designs including the K8 and the K9. Now this was the first I'd heard them talk publicly about the K9 so I found it very interesting. They mentioned the K8 would have 8 layers of metal, as the K7 had 6 layers this would seem to allow for more efficient routing. They said the K9 should tape out in 2003 and ship in the summer of 2004. Their number one priority along with increased performance and frequency when designing the K9 was power consumption. Apparently they are putting power limits on each section of the design. They went into some more detail but I didn't take notes on it. Good times ahead

 

[diehlr]

A lot of those transistors are probably devoted to cache since the Hammer is supposed to have a lot of it. The physical layout for cache is more dense than other logic like an ALU, I think. I don't know how much of an overall impact this would make on the average density of the transistors, but probably at least some.

 

[ElFenix]

last i heard hammer is 256K l2, and probably 128K l1 again. and from intel's 6.5 meg 300 million transistor sram they showed its about 42 million transistors for half a meg of cache. which gives p4 about 13 million for the rest of it (of course theres more cache in there, but its onyl a couple million transistors). if hammer has 384K then thats ~32 million for cache, and a whole ton for other logic. hmmm... thats a frickin' lot of ALU.

 

[2cool4u]

interesting article but here's a link that works

 

[Degenerate]

what about builind upwards? like layers? that would increase the number of transistors without increasing the surface area, by much.