I have just received a new new Patriot Memory Viper Steel PVS416G440C9K paired with a 3900x and a B550 MSI Itx gaming motherboard. I did not want to do some crazy OC so played with timings at around 1.38v. My original timings on the right resulted in memtest86 errors so decided to loosen it a little bit more by reducing the TFaw and TWr as per the DRAM calculator (basically going for a safe preset rather than fast). And the impact it had on membench time was ridiculous which either means a. it's unstable at that looser timing (did memtest86 on this settings and no errors)OR b. changing the TFaw and TWr from 12 to 24 have a massive impact.
to summarise:
Left Pic: Looser TFaw and TWr no memtest errors, stable but huge membench performance degradation. and Right Pic: Tighter TFaw nad TWr but memtest errors, and was unstable (esp gaming).
It doesn't end there. I decided to go back to tighter timings and this time follow the DRAM calculator's fast settings for the sub-timings (especially tRFc) closely but kept the main timings to CL15 with trCDRD at 16 (TRas and TRc also manual values to reflect) because with CL14 main timings the system doesn't really boot at 1.38v and not really keen on putting more voltage/stress.
And guess what, these even tighter timings at the same voltage actually produces no errors (2x 4 passes memtest, karhu, etc. and passes stability testing. I'm getting some really impressive benchmark results... Is it a case that the CPU/RAM prefer the tighter timings??? It just defies logic! I mean... WTF??!!
above: Stable system with tighter timings at the same voltage. Although increased VDDP and VDDG by 0.1v each as they were reading 0.895 and 0.945 respectively to match the recommended 0.9 and 0.95 minimum. SOC is 1.1 for all cases.
to summarise:
Left Pic: Looser TFaw and TWr no memtest errors, stable but huge membench performance degradation. and Right Pic: Tighter TFaw nad TWr but memtest errors, and was unstable (esp gaming).
It doesn't end there. I decided to go back to tighter timings and this time follow the DRAM calculator's fast settings for the sub-timings (especially tRFc) closely but kept the main timings to CL15 with trCDRD at 16 (TRas and TRc also manual values to reflect) because with CL14 main timings the system doesn't really boot at 1.38v and not really keen on putting more voltage/stress.
And guess what, these even tighter timings at the same voltage actually produces no errors (2x 4 passes memtest, karhu, etc. and passes stability testing. I'm getting some really impressive benchmark results... Is it a case that the CPU/RAM prefer the tighter timings??? It just defies logic! I mean... WTF??!!
above: Stable system with tighter timings at the same voltage. Although increased VDDP and VDDG by 0.1v each as they were reading 0.895 and 0.945 respectively to match the recommended 0.9 and 0.95 minimum. SOC is 1.1 for all cases.