Does anyone see any reason why the graphics chip on an Opteron system could not use one of the three available HT buses to communicate with the processor? To me it just seems a huge waste to manufacure a GPU that has uses AGP and a bridge chip to link it to the CPU. Also, AGP 8x runs at 2.1GB p/s and a 16 bit HyperTransport link running full throttle could over tripple that bandwith, and you would eliminate the extra cost of an AGP bridge. I realize theoretically PCI Express would be faster @ 8 GB p/s, but I would wonder why bother with a bridge/bus when your can just connect the GPU and CPU directly. Anyway, just a thought.
Graphics over HyperTransport
- Thread starter lexxmac
- Start date
Because it's unprofitable to only build a card that works in Opterons, and not in the various K7 or Intel-based systems, probably.
If you can find the block diagrams for the GPU architechtures, and examine the GPUs that support the old PCI graphics and their AGP counter parts (I know the Mobile Radeon 9000 does, I've got a bunch of info on it), the GPU has a unit for communicating over whatever bus is used. Just the same way, an existing GPU could be outfitted with a unit to communicate over hypertransport. I realize that there might be added expense in producing a totally seperate die, but that's part of the porcess in developing a new technology. Once you can prove that it would work better than an existing solution, you could begin to produce cards. And since hypertransport is royalty free and is a good idea, who is to say that intel won't produce a cpu in the future with hypertransport links and an on-die memory controller. Is that idea patented? Apparently not, as the transmeta efficeon already has both of those features.
From another site's FAQ
It's not that they can't do it, it's that there isn't currently any reason to do so.
So, to answer your question, you can use one of the HT links for AGP. Motherboards that don't use the above solution are using a different chipset (Nforce3, Via, etc.). Their chipsets connect to the cpu using their own proprietary methods which they think are better. Since, as you pointed out, AGP can't saturate an entire HT link, it would be wasteful to set aside 1/3 of your bandwith for such a purpose. The third party solutions combine AGP functionality on their chips with other things (SATA, GigE, PCI, etc.) at a cheaper price than AMD's solution.
It's not that they can't do it, it's that there isn't currently any reason to do so.
I apologize, I didn't make myself totally clear. I realize that you can use one othe hypertransport links for an AGP bridge. What I really meant is to use hypertransport as the direct connet, no AGP involved, and possibly going as far as having a "hypertransport slot" instead of an AGP slot so the graphics processor could have all of that 6.4 GB p/s of bandwidth. I'm trying to avoid routing the graphics traffic through another chip. That saves money and board real-estate. Also, hypertransport is serial, and AGP is parallel, so eliminating AGP altogether cuts down on board traces, which means there is less of an opportunity for interferance, not to mention easier to manufacture, especially say on a notebook board.
Considering that a) most video cards don't even come near saturating AGP8X, let alone HT, and b) PCI Express will likely be available within a year, this seems like a very wasteful move. We finally have a good, solid standard established for high-speed video cards, and now you want another one? It would be a lot of expense for very little (if any) gain, and the cards would be obseleted by PCI Express sooner rather than later.
Why would PCI express make it obsolete? And again, why route everthing though another IC?! PCI express is a step in the wrong direction. AGP was created so that it had a seperate way to communicate with the CPU. PCI express is just a glorified legacy PCI that's been serialized, and some speed improvements. But Intel doesn't want to learn from their own mistake that they made with the original PCI bus and graphics. The GPU will (or at least should) eventually connect directly to the CPU. And yes, PCI express is faster, on paper. But, the PCI Express hub connects to the CPU over the FSB in all the diagrams Intel has released. With the current P4s running an 800FSB, that limits all traffic to the CPU to 6.4GB p/s. I look to see PCI express go the same way as the VESA local bus.
The GPU hardly ever needs to talk to the CPU -- it needs to talk to the memory, using DMA to get texture and model data that won't fit onboard (which is becoming less and less of an issue, since new video cards have 128-256MB of memory, and we're moving towards vertex/pixel shading over multitexturing). What is your insistence on hooking the GPU up to the CPU? What exactly does that do for you? Putting it on the FSB is the most logical place for it. And people are already overclocking *current* front side busses to over 250Mhz -- I'm sure Intel will improve on that in the next generation of CPUs.
But disregarding that, PCI Express is more than "glorified legacy PCI". It's more like SATA or Fibre Channel than the original PCI spec. And even if it *was* just a glorified PCI bus, it would be a REALLY FAST glorified PCI bus. I just don't see what the benefits of using HT are, other than more bandwidth -- which PCI Express offers, along with the ability to (for the first time in recent history) only have one kind of expansion card in your PC!
But disregarding that, PCI Express is more than "glorified legacy PCI". It's more like SATA or Fibre Channel than the original PCI spec. And even if it *was* just a glorified PCI bus, it would be a REALLY FAST glorified PCI bus. I just don't see what the benefits of using HT are, other than more bandwidth -- which PCI Express offers, along with the ability to (for the first time in recent history) only have one kind of expansion card in your PC!
Since hammer systems don't have a front side bus to speak of, and the memory controller is on the CPU, connecting to the CPU is connecting to the Memory. Remeber also that an Opteron has 3 hypertransport links (6.4x3 =19.2). So until Intel can produce a 600MHz front side bus, the crown goes to hypertransport. Did I mention its royalty free (unlike Intel's FSB)?
you have the PCI express controller there anyway for all the other devices in the computer... what do you lose by using it?
I can see that I misunderstood your original question, but the points I made are still valid.
You only have 3 HT links available. In multiprocessor systems you will be using some or all of them for inter-processor communication. Taking one of them away for dedicated video use will limit what you can do with the rest of the system. It may not be a bad idea for a special purpose machine, but most computers will need some peripherals in order to be useful. It isn't whether or not PCI Express is the best solution for video, it's whether PCI Express is a good solution for the peripherals customers will want on their machines. Since customers will want PCI Express for other things, then you might as well move your video over and free up the HT link for other purposes.
So, I'm pretty sure you can have your video connect through HT directly, but I don't think there is enough market for anyone to do so.
You only have 3 HT links available. In multiprocessor systems you will be using some or all of them for inter-processor communication. Taking one of them away for dedicated video use will limit what you can do with the rest of the system. It may not be a bad idea for a special purpose machine, but most computers will need some peripherals in order to be useful. It isn't whether or not PCI Express is the best solution for video, it's whether PCI Express is a good solution for the peripherals customers will want on their machines. Since customers will want PCI Express for other things, then you might as well move your video over and free up the HT link for other purposes.
So, I'm pretty sure you can have your video connect through HT directly, but I don't think there is enough market for anyone to do so.
It may make sense on rendering clusters that display to a panel of tiled displays, like that dohickey they made in Kentucky. I doubt there will be a significant performance improvement to justify the manufacture of a custom motherboard and video chipset.
You're right about the Opteron platform -- I was talking more in general terms about the relationship between the CPU and GPU. In an Opteron system you are, for all practical purposes, using a HT link for it anyway, just with a chipset in the middle to manage the AGP/HT stuff. But as was pointed out, you probably won't be able to dedicate more than one link for the graphics, at least in multiway systems, or if other functions (like SATA) are tied to it.
Being royalty-free is nice, but they still have to develop graphics cards for Intel chipsets. I just don't see the miniscule advantages of HT being enough to not use PCI Express, especially considering the costs of producing and marketing several different interface versions of the same cards. The scalability and -- more importantly, IMHO -- the fact that you no longer will have a whole separate kind of bus just for your graphics card beat out any slight speed increase you may get.
Think about the graphics processor as a specialized second CPU, with its own sets of commands. Would you put a second opteron on a bus where it competes for traffic with other devices communicating with the main cpu? The flaw is really in having front side bus in the first place. AMD has already proved having the memory controller on the processor die has significant advantages. Hypertransport is a way to communcate with the CPU now that the front side bus is gone. Reguardless of the arguments, I am absolutely sure it would work and has significant advantages.
In a multiprocessor system you will have four links available for things besides the CPUs (that's more in a multi-cpu system, not less). Here's a wonderful diagram 
http://www.amd.com/us-en/assets/content_type/DownloadableAssets/AM190_briefv3.pdf
http://www.amd.com/us-en/assets/content_type/DownloadableAssets/AM190_briefv3.pdf
Originally posted by: lexxmac
In a multiprocessor system you will have four links available for things besides the CPUs (that's more in a multi-cpu system, not less). Here's a wonderful diagram
http://www.amd.com/us-en/assets/content_type/DownloadableAssets/AM190_briefv3.pdf
Let me be the first to say you're sounding a hecka lot like an AMD fanboy. No, that's not a compliment. Yes, I'm currently typing this on an Athlon. And, yes, I do acknowledge the technical prowess of the lackluster little company that's struggling. And, no, I do not consider Intel to be the spawn of the Devil. Maybe a succubus.
Anyway, while the Opteron CPUs have four links available, only three are HT. The fourth is the memory bus. If you want to get technical, it's a dedicated memory bus. In other words, you cannot hook up anything else besides memory. Or, put in another way, it's designed solely for use with memory. It won't work with anything besides memory. In fact, it won't work with anthing besides DDR ord DDR-II and even the DDR-II part is still questionable.
The main problem with designing a graphics controller to interface directly with HyperTransport is the loss of the HT link. If you dedicate one HT link to the graphics card, one CPU would be left with only two HT links for multiprocessing and peripherals. That means that in the lovely diagram you just linked, ALL peripherals besides the graphics card would be routed through one HT link on one of the four CPUs.
The second problem is the severe overkill. Considering how little the graphics card would utilize the phenomenal bandwidth, that is one big waste. An AGP tunnel or a PCI-Express or even PCI-X interface would make more sense. This is, of course, unless you want to undo almost a decade of graphics development and reduce the memory size on your graphics card. Only then would you find a compelling reason to hook up your graphics solution to a high speed dedicated bus to main memory, which, btw, also means you're taking up main memory that could be used elsewhere such as, I don't know, the game you're trying to play.
Oh, yes, one more thing. If you decide to build a graphics solution hooked up to HT, wtf are you going to do with poor saps with Athlon64 systems with only one HT link in the entire system? You'll probably build a PCI-Express or AGP card. Well, since they both cost the same to design and implement, why the deleted would you decide to double the cost of your overhead just to satisfy the small percentage of folks who happen to have workstations or servers with Opterons? Servers and workstations make up something on the order of 5% of computers. Of that category, less than 10% or so use Opterons. Of those that use Opterons, workstations comprise something like 10%. So you're talking about catering to 10% of less than 10% or 5% of the entire population of computers in the world. That type of mentality led to the PC boom of the late 90's, and we all know how well that turned out.
So, yes, HT can be used for graphics. Yes, HT has more bandwidth that AGP. However, no, I don't think we'll be seeing HT based graphics cards in mass production anytime soon.
I realize that each opteron CPU has only three hyper transport links. But when you connect two of opterons together for a multiprocessor system, both CPUs use one link to connect each other, so if each CPU has 3 links (2 CPUs x 3 links= 6 total), the links on the second cpu don't just disappear. There are four links available as long as you have more than one CPU. Did you even look at the diagram I posted a link to? As for the guys with an Athlon64 system, I know that it would leave them out in the cold, I just thought it was an idea I'd throw out for discussion. I'm not going to argue about it anymore. I know I'll probably never see a HT graphics card in mass production; I knew that before I started the thread.
Yes, I did look at the diagram. The whole point of my rant was not to say it's not technically possible, but to say it's technically inefficient and at this point tantamount to pulling a trick out of 3dfx's bag. The equivelent of a HT connected video card would be a Voodoo II with an AGP 3.0 interface. Yes, you can do it, yes, it's a damn waste of bandwidth, and yes, you've left out more than half the equation.
I know its inefficient as most consumers have no idea what AGP is or that it exists, and would never know the difference. Although it would be huge waste of bandwidth with a GPU that was designed to use an AGP bus, I would wonder if there might be some ways to take advantage of the extra bandwith, say by utilizing the vertex/shader units or OpenGL more in the GUI itself or for MPEG de/encoding. I'm sure some use could be found that the extra bandwidth could be used for. The four panel display in the comdex article just posted might be a good application also. About 3dFX, I'm not terribly sure what exactly they did with the Voodoo II, as I have not been following graphics for that long. So if you know a good summary about it, I'd be happy to read it, although I'll probably go look for one in a minute.
AGP graphics chips running on PCI cards is a matter of AGP being VERY similar to PCI, to the amount that any AGP chip that still can do 2x AGP mode (3.3V signalling) can gluelessly connect to a PCI bus - as it is, no tricks required.
Why not make directly HT attached graphics chips? Well, for one, because PCI-Express is almost here and has already been embraced as the next generation solution for this; and secondly, because HT was never designed as a peripheral bus travelling slots and cards and all that. Thirdly, as all the others had said already, it's a huge waste of bandwidth better used elsewhere.
Why not make directly HT attached graphics chips? Well, for one, because PCI-Express is almost here and has already been embraced as the next generation solution for this; and secondly, because HT was never designed as a peripheral bus travelling slots and cards and all that. Thirdly, as all the others had said already, it's a huge waste of bandwidth better used elsewhere.
I know that video was presented at IDF, but what about AMD systems? All AMD64 systems contain the memory controller on the CPU die. Hypertransport is the only way to connect to the CPU or main memory controller. So, if the GPU wants to access RAM or the CPU caches, it must eventually travel over one of the hypertransport buses. I realize that a PCI Express controller that connects up to hypertranport is what is likely to happen. PCI express makes wonderful sense with the Intel system architecture. The HT enabled PCI express chipset will happen so that everyone can use PCI express video cards. Still, I think that it would be interesting. More later...
Current 8x AGP implementations on AMD64 demonstrate quite clearly that the HyperTransport path into the CPU's RAM controller is plenty fast enough for texture access by the graphics card. (btw, the GPU cannot access the CPU caches ever, anywhere.)
We'll very possibly see HyperTransport attached PCI-Express tunnels, just like we've got AGP and PCI-X tunnel chips now. That's the fun in having the RAM controller in the CPU and making the chipset do nothing but I/O - you can modularize and swap in and out all kinds of I/O busses, even the very fast ones, without having to respin a complicated chip with high-speed CPU front side and RAM busses every time a new I/O bus needs to be implemented.
Make a HT-to-Whatever tunnel for whatever I/O bus is getting relevant, shuffle, mix, and match with the HT attached chips that already exist, stir in a southbridge, and you're set. The CPU chip itself will handle the core business.
We'll very possibly see HyperTransport attached PCI-Express tunnels, just like we've got AGP and PCI-X tunnel chips now. That's the fun in having the RAM controller in the CPU and making the chipset do nothing but I/O - you can modularize and swap in and out all kinds of I/O busses, even the very fast ones, without having to respin a complicated chip with high-speed CPU front side and RAM busses every time a new I/O bus needs to be implemented.
Make a HT-to-Whatever tunnel for whatever I/O bus is getting relevant, shuffle, mix, and match with the HT attached chips that already exist, stir in a southbridge, and you're set. The CPU chip itself will handle the core business.
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