GloFo and TSMC FinFet News

[Idontcare]

Saw both of these articles over on EETimes, figured people would be interested in them but wasn't sure where best to place them in terms of existing threads.

If having them in another thread is preferred, versus having a new thread dedicated to finfet news, let me know and I'll move the links appropriately.

TSMC breaks ground for FinFET fab

Foundry Taiwan Semiconductor Manufacturing Co. Ltd. has held a groundbreaking ceremony for a fab module at its Fab 14 gigafab at the South Taiwan Science Park in Tainan, Taiwan. The phase-six module is expected to be TSMC's first fab to mass produce 16-nm FinFET circuits in 2014.

Building work for phase six of the Fab 14 gigafab is not due to start until 2013 as part of a $17 billion capacity expansion scheduled for the next five years, according to a Taipei Times report.

"The factory will be the world's first 12-inch factory producing 20-nanometer system-on-chips and the first 16-nanometer FinFET chip manufacturing site for TSMC," the report quoted TSMC co-chief operating officer Chiang Shang-yi, as saying.

Source

Globalfoundries' FinFET wafers set to roll

The first multiproject wafer runs for customers testing Globalfoundries' 14-nm FinFET manufacturing process technology could start as soon as the first quarter of 2013, according to Mike Noonen, executive vice president of worldwide marketing and sales at the foundry chip maker.

When asked if the 14XM process was still liable to receive tweaks as a process, or even to major changes such as the use of silicon-on-insulator (SOI) wafers as a starting point to improve manufacturability Noonen said: "14XM is a bulk process."

However, Noonen added that Globalfoundries does have experience in other process technologies that make use of SOI wafers. "We have additional strong alliances on fully-depleted SOI. We are the manufacturing partner for STMicroelectronics for FDSOI at 28-nm and 20-nm. We have aligned ourselves with the thought leaders in all the manufacturing processes."

FDSOI uses planar transistors but it could be that logical road-map for both process technologies merges at some point in the future. There has been discussion as to whether the use of SOI can reduce the variability of FinFETs and improve performance at 14-nm. Some think it can while others have cited potential problems with floating-body effects and self-heating.

Source

Confirmation that 14nm-XM is bulk silicon, not SOI and not FDSOI.

Which surprises me because the 14nm-XM is planned for "xtreme mobility" in which case lowering the leakage is all the more paramount, exactly what SOI and FD-SOI address.

At any rate, we are likely to continue to see near-simultanous PR from these two foundries going forward as it relates to their respective Finfet progress, so we may as well have a thread about both IMO.

I know both GloFo and TSMC have put out roadmaps for this, if I can locate those images then I'll add them to the thread. If anyone else has them handy and can beat me to it, I'd appreciate the help :thumbsup:

 

[mrmt]

Confirmation that 14nm-XM is bulk silicon, not SOI and not FDSOI.

Which surprises me because the 14nm-XM is planned for "xtreme mobility" in which case lowering the leakage is all the more paramount, exactly what SOI and FD-SOI address.

SOI wafers brings more 10% in wafer costs plus lower yields, not exactly exciting for the ARM ecosystem. Also Intel achieved full depletion with FinFet, why wouldn't GLF follow the same route?

 

[Fjodor2001]

So when can we expect these TSCM and GloFo fabs to actually start producing chips?

And how will it compare to Intel's 14 nm process?

 

[AtenRa]

SOI wafers brings more 10% in wafer costs plus lower yields, not exactly exciting for the ARM ecosystem. Also Intel achieved full depletion with FinFet, why wouldn't GLF follow the same route?

No, the Fins are not Fully Depleted on Intel's 22nm Tri-Gate. But they are with FD-SOI.

 

[SocketF]

SOI wafers brings more 10% in wafer costs plus lower yields,

Yes but the SOI people claim, that you will safe several process steps in return, which results in lower total costs and probably also faster fabbing.

Not sure though, if these claims are true, or just marketing bs.

 

[mrmt]

No, the Fins are not Fully Depleted on Intel's 22nm Tri-Gate. But they are with FD-SOI.

Intel info says they are full depleted

http://download.intel.com/technology/silicon/tri-gate-transistor-conference-paper-0603.pdf

 

[AtenRa]

Intel info says they are full depleted

http://download.intel.com/technology/silicon/tri-gate-transistor-conference-paper-0603.pdf

The Gate is Fully Depleted, the Fins are not.

 

[Haserath]

Why would anybody really want to do FD-SOI over bulk for mainstream anyway?

The chip may be slightly better in the end on average, but the cost goes way up. Might as well just implement bulk nodes as far as you can, then move to something more exotic when required.

Costs less= faster node switching=more competitive&better products in less time

 

[Idontcare]

The Gate is Fully Depleted, the Fins are not.

I think you are confusing the nomenclature and labels for the vernacular.

Intel refers to its transistor designs by the number of gates, but you don't "deplete the gate", you deplete the channel.

If you read the paper you can see where the authors use the labels interchangeably. This might seem to be in error, however the paper was written for a target audience that would know to equate these labels a priori.

 

[AtenRa]

Well, since the channel is thru the Fin and the Fin is not isolated from the substrate how is it Fully Depleted ??

 

[Idontcare]

Well, since the channel is thru the Fin and the Fin is not isolated from the substrate how is it Fully Depleted ??

The finfet described in mrmt's linked pdf is on buried oxide (SOI), see figure 4, it is isolated and fully depleted.

I was addressing the disconnect in your comment versus mrmt's link.

That said, the 3d xtors Intel has in production are obviously not fully depleted, which I am guessing is what you are speaking to? Maybe you two are talking past each other and I am not helping?

edit: Possibly unrelated, but this article on fully-depleted xtor designs (and their tradeoffs) is actually a pretty cool little article.

The era of fully-depleted devices

 

[AtenRa]

hmm ok got it,

I was talking about Intels FinFet Tri-Gate which is not FD.

You are right, the xtor in the pdf is FD.

 

[Idontcare]

hmm ok got it,

I was talking about Intels FinFet Tri-Gate which is not FD.

You are right, the xtor in the pdf is FD.

And it would appear that both TSMC and GloFo are planning to go the same route Intel did - explore the benefits of FD-Finfet for research papers but put Finfet-bulk into production.

 

[mrmt]

That said, the 3d xtors Intel has in production are obviously not fully depleted, which I am guessing is what you are speaking to?

IDC, would you explain this part? I remember seeing a lot of papers and presentations from Intel stating that their 22nm transistors are full depleted.

Here for example:

http://download.intel.com/newsroom/kits/22nm/pdfs/22nm-Details_Presentation.pdf

On slide 14 they refer explicitly to their 22nm as fully depleted. That presentation bears the name of Kaizad Mistry, the 22nm program manager.

My guess is that there is a small difference in the criteria you two are using for calling the transistor fully-depleted.

 

[Idontcare]

IDC, would you explain this part? I remember seeing a lot of papers and presentations from Intel stating that their 22nm transistors are full depleted.

Here for example:

http://download.intel.com/newsroom/kits/22nm/pdfs/22nm-Details_Presentation.pdf

On slide 14 they refer explicitly to their 22nm as fully depleted. That presentation bears the name of Kaizad Mistry, the 22nm program manager.

My guess is that there is a small difference in the criteria you two are using for calling the transistor fully-depleted.

Say wha!? How about that, I had not dug into the matter before to see what Bohr was referring to in all those pdfs until now. I had always assumed when Intel spoke of "fully-depleted finfets" it was in reference to the experimental ones with the buried oxide discussed in their research papers.

But nope, you are completely correct. The finfet-bulk xtors that Intel put into production for 22nm are indeed fully-depleted.

I hunted around for a basic explanation of "how can this be" and oddly enough TheRegister of all places had the most understandable explanation:

Planar processors are hell to make fully depleted. In their traditional state, there's a lot of room in the silicon substrate to house errant voltages. You can, however, add an oxide insulator below the source and the drain to create what's called a partially depleted silicon-on-insulator (PDSOI) design.

You can go all the way to fully depleted (FDSOI) without going FinFET by depositing an extremely thin SOI layer on top of the oxide – but reaching full depletion this way is quite expensive. According to Bohr, baking a chip this way adds at least 10 per cent to the total wafer cost.

Tri-Gate, by comparison, is cheap. "Another nice thing about the Tri-Gate devices," Bohr says, "is that they're not that expensive to add. Compared to a planar version of 22 nanometers, Tri-Gate transistors add only about 2 to 3 per cent cost to the finished wafer."

The Tri-Gate way of reaching full depletion is to stick that silicon fin up into the gate, have the inversion layer on both sides and the top of the fin, with the high-k metal oxide of the gate snug against the inversion layer. Presto – no room for nasty voltages to accumulate, plus the larger wrap-around inversion layer and metal-oxide interface allow for more current, and thus better performance

Source

So, no need for the buried oxide in order to operate in fully depleted mode. Hadn't realized that before. I'm assuming then that finfet-soi merely adds improved reduction in substrate leakage and not much else?

 

[mrmt]

I'm assuming then that finfet-soi merely adds improved reduction in substrate leakage and not much else?

I always understood that SOI is a mean to achieve depletion, if you can achieve that through FinFet then what's the point of SOI?

Even if it does improve leakage when combined with finfet, is it worth the cost? The most commercially successful foundries didn't embrace SOI before finfet, why would them now that they have a much cheaper way to fight leakage?

Btw, who is putting forward finfet FD-SOI? Because until now I didn't see anything but press releases and the habitués in tech forums, but not a single commercial foundry committed to a FD-SOI Finfet node.

 

[Idontcare]

I always understood that SOI is a mean to achieve depletion, if you can achieve that through FinFet then what's the point of SOI?

Even if it does improve leakage when combined with finfet, is it worth the cost? The most commercially successful foundries didn't embrace SOI before finfet, why would them now that they have a much cheaper way to fight leakage?

Btw, who is putting forward finfet FD-SOI? Because until now I didn't see anything but press releases and the habitués in tech forums, but not a single commercial foundry committed to a FD-SOI Finfet node.

Yeah that was my surmises as well. STMicro has been big on pushing the FD-SOI angle, and GloFo PR is happy to share the limelight as well. But outside of basic research I haven't seen or heard of anyone intending to put them into production when combined with Finfets.

Pretty sure the folks at Soitec are in full-on scramble mode at the moment.

 

[mrmt]

Pretty sure the folks at Soitec are in full-on scramble mode at the moment.

I found this on their last financial report:

4.1. Group’s activities and situation

Total sales declined by 19.9% in the first half of 2012, with total revenues amounting to 130.2 million Euros compared to 162.5 million Euros during the first six months of the previous fiscal year and compared to 160.8 million Euros in the second half of the previous fiscal year. During the first half of 2012-2013, the Group recognized an operating loss of 70.2 million Euros, compared to 8.5 million Euros in the first half of the preceding fiscal year and 37.4 million Euros in the second half of the previous fiscal year.

And they paint a very grim picture for their future:

5. Information regarding tendencies

In the Electronics sector, global end-customer consumption remains uncertain, especially for high performance PC-related markets, but demand for mobility products remains robust (tablets, mobile phones) and this impetus drives technological changes for chip manufacturers.

Soitec's major customers for 300 mm wafers face intense competition and have announced their willingness to propose new solutions based on standard silicon technologies. At the same time, Intel's technological roadmap takes a three-pronged approach regarding transistor structure for 20nm nodes and below. While Soitec has developed SOI-based solutions which address both planar and non-planar designs for 20 nm nodes and below, these solutions have yet to be adopted on a large scale in order to off-set the current trend observed for traditional 300mm SOI markets.

ST Microelectronics' recent announcement concerning fully-depleted SOI based solutions demonstrates the value of Soitec's technological arsenal, but needs to translate into mass adoption by several other industry players in order to generate sufficient revenue for Soitec, directly or from royalties paid by its licensee, Shin Etsu Handotai with which Soitec recently renewed its license agreement

Usually we see this kind of statements when the company is describing the risks and worst case scenarios, but this kind of perspective and language on assessments is unusual to say the least.

Maybe we could try to send this to xbitlabs to see how they are going to spin positively these statements.

 

[piesquared]

GlobalFoundries: 14nm-XM Process Tech Two Times More Power-Efficient Than 28nm.

GlobalFoundries: 10nm Process on Track for 2015, 7nm Fabrication Technology Due in 2017.

Global Foundries lays out their FinFET plans

Global Foundries expands their IP menu

Well, there's a ton of new information from the Common Platform Tech Forum. 2014 does indeed appear to be process parity for foundries and IDM's.

 

[CHADBOGA]

GlobalFoundries: 14nm-XM Process Tech Two Times More Power-Efficient Than 28nm.

GlobalFoundries: 10nm Process on Track for 2015, 7nm Fabrication Technology Due in 2017.

Global Foundries lays out their FinFET plans

Global Foundries expands their IP menu

Well, there's a ton of new information from the Common Platform Tech Forum. 2014 does indeed appear to be process parity for foundries and IDM's.

The only place where parity exists, is in Powerpoint slides and in the minds of the severely deluded.

 

[Idontcare]

GlobalFoundries: 14nm-XM Process Tech Two Times More Power-Efficient Than 28nm.

GlobalFoundries: 10nm Process on Track for 2015, 7nm Fabrication Technology Due in 2017.

Global Foundries lays out their FinFET plans

Global Foundries expands their IP menu

Well, there's a ton of new information from the Common Platform Tech Forum. 2014 does indeed appear to be process parity for foundries and IDM's.

Thanks for posting up these links piesquared :thumbsup:

I think you might have a copy-paste error on the 7nm link - pretty sure you meant this one: http://www.xbitlabs.com/news/other/...2015_7nm_Fabrication_Process_Due_in_2017.html

FD-SOI didn't even get an honorable mention, must really be a fringe process from their perspective.

 

[ShintaiDK]

So when can we expect these TSCM and GloFo fabs to actually start producing chips?

Something like 1½-2 years later than the dates they show. Unless delayed.

 

[piesquared]

Thanks for posting up these links piesquared :thumbsup:

I think you might have a copy-paste error on the 7nm link - pretty sure you meant this one: http://www.xbitlabs.com/news/other/...2015_7nm_Fabrication_Process_Due_in_2017.html

FD-SOI didn't even get an honorable mention, must really be a fringe process from their perspective.

Yes, fixed.

There's probably 100 articles over the last few days coming out of the CPTF, I only a posted a few. Here's an FD-SOI article.

Globalfoundries commits to FDSOI process

 

[mrmt]

Well, there's a ton of new information from the Common Platform Tech Forum. 2014 does indeed appear to be process parity for foundries and IDM's.

Do you believe in Globalfoundries and IBM foundry announcements? I have an investment opportunity for you.

 

[podspi]

We can hope, but have we even seen any 28nm chips from GF yet?

Would be interesting if GF becomes anything other than a parasite feeding off of AMD, but it hasn't happened yet...