Search Results matching the keyword parity
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Give me an uber geek super description of how parity works.
- Thread starter SoylentGreen
- Start date
Cogman
Lifer
- Sep 19, 2000
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you asked for it 
as a noun
Main Entry: 1par·i·ty
Pronunciation: 'par-&-tE
Function: noun
Inflected Form(s): plural -ties
Etymology: Latin paritas, from par equal
Date: circa 1609
1 : the quality or state of being equal or equivalent
2 a : equivalence of a commodity price expressed in one currency to its price expressed in another b : equality of purchasing power established by law between different kinds of money at a given ratio
3 : an equivalence between farmers' current purchasing power and their purchasing power at a selected base period maintained by government support of agricultural commodity prices
4 a : the property of an integer with respect to being odd or even <3 and 7 have the same parity> b (1) : the state of being odd or even used as the basis of a method of detecting errors in binary-coded data (2) : PARITY BIT
5 : the property of oddness or evenness of a quantum mechanical function
6 : the symmetry of behavior in an interaction of a physical entity (as a subatomic particle) with that of its mirror image
as a diffrent noun
Main Entry: 2parity
Function: noun
Etymology: -parous
Date: 1878
: the state or fact of having borne offspring; also : the number of children previously borne
and a parity bit
Main Entry: parity bit
Function: noun
Date: 1957
: a bit added to an array of bits (as on magnetic tape) to provide parity
Hope these are good enough.
as a noun
Main Entry: 1par·i·ty
Pronunciation: 'par-&-tE
Function: noun
Inflected Form(s): plural -ties
Etymology: Latin paritas, from par equal
Date: circa 1609
1 : the quality or state of being equal or equivalent
2 a : equivalence of a commodity price expressed in one currency to its price expressed in another b : equality of purchasing power established by law between different kinds of money at a given ratio
3 : an equivalence between farmers' current purchasing power and their purchasing power at a selected base period maintained by government support of agricultural commodity prices
4 a : the property of an integer with respect to being odd or even <3 and 7 have the same parity> b (1) : the state of being odd or even used as the basis of a method of detecting errors in binary-coded data (2) : PARITY BIT
5 : the property of oddness or evenness of a quantum mechanical function
6 : the symmetry of behavior in an interaction of a physical entity (as a subatomic particle) with that of its mirror image
as a diffrent noun
Main Entry: 2parity
Function: noun
Etymology: -parous
Date: 1878
: the state or fact of having borne offspring; also : the number of children previously borne
and a parity bit
Main Entry: parity bit
Function: noun
Date: 1957
: a bit added to an array of bits (as on magnetic tape) to provide parity
Hope these are good enough.
basically, there exists an algorithm that for every n chunks of data, you can create n+1 chunks of data such that ANY n chunks of data can recreate the original data.
For example, if you have 21 100 GB hard drives in a RAID 5 configuration, you can store 2 TB(20x100Gb) of data on those drives and if any one of the drives fail, you can rebuild the data again.
This is incredibly useful as you need to have two drives fail within a x hour time period before all your data gets hosed. The chances of that happeneing are infitesmal. If you had two parity drives, you would need 3 drives failing within 2x hours of each other and those chances are truely astronomical.
For example, if you have 21 100 GB hard drives in a RAID 5 configuration, you can store 2 TB(20x100Gb) of data on those drives and if any one of the drives fail, you can rebuild the data again.
This is incredibly useful as you need to have two drives fail within a x hour time period before all your data gets hosed. The chances of that happeneing are infitesmal. If you had two parity drives, you would need 3 drives failing within 2x hours of each other and those chances are truely astronomical.
normal byte
10010110
the same byte with parity
10010110-0
if one of the 9 bit is lost you can validate the byte using the parity bit
100x0110-0
if the parity bit is 0 the total number of 1 in the byte must be even
if the parity bit is 1 the total number of 1 in the byte must be odd
with only this information you cannot rebuild the byte (error correction) but you can detect the error (error detection)
10010110
the same byte with parity
10010110-0
if one of the 9 bit is lost you can validate the byte using the parity bit
100x0110-0
if the parity bit is 0 the total number of 1 in the byte must be even
if the parity bit is 1 the total number of 1 in the byte must be odd
with only this information you cannot rebuild the byte (error correction) but you can detect the error (error detection)
How do you tell where on bye ends and the next begins?
There has to be 4 on and 4 off per byte? That's inefficient.
an application of partity
10 imprisioned men are told that in the morning they will be blind folded, lined up single file and a hat will be placed on their head. The hat will be black or white, totaly random for each man. Once in line with the hats in place The blindfolds will be removed and starting from the man at the back of the line each must guess the color of his hat. If he is correct he will live, incorrect he will be shot. They may converse only till the blindfold is put on in the morning. What shceme can they use to maximize the survival rate. No other form of signal may be used.
The answer is that there is a 50-50 chance that one man will die.
They agree the night before that the end man will count the black hats in front of him, if the number is even he says White, if Odd he says black, He has a 50-50 chance of dying. The man in front of him now knows that if he hears white and sees an ODD number of black hats his must be black each man can now KNOW the color of his hat as the man behind reports his color.
This is parity
Now do a search on Parity on this site.
10 imprisioned men are told that in the morning they will be blind folded, lined up single file and a hat will be placed on their head. The hat will be black or white, totaly random for each man. Once in line with the hats in place The blindfolds will be removed and starting from the man at the back of the line each must guess the color of his hat. If he is correct he will live, incorrect he will be shot. They may converse only till the blindfold is put on in the morning. What shceme can they use to maximize the survival rate. No other form of signal may be used.
The answer is that there is a 50-50 chance that one man will die.
They agree the night before that the end man will count the black hats in front of him, if the number is even he says White, if Odd he says black, He has a 50-50 chance of dying. The man in front of him now knows that if he hears white and sees an ODD number of black hats his must be black each man can now KNOW the color of his hat as the man behind reports his color.
This is parity
Now do a search on Parity on this site.
Well, if it's totally random, there's a 1/256 chance that all but the hat in back are the same color and everyone dies.
I think that only works if ther are the same number of each hat color (at least that's how it was when I heard it).
They could also interpolate as the other men behind them speak their hat color.
Still, the first guy gets it in the shorts.
Reread the puzzel and the solution. I meant exactly what I said and gave you the solution. Read it and work through it.
K6 had a good explanation of parity...
It is nothing more than a checksum bit (or bits) that lets the receiver know if the data package received has been corrupted. The concept of parity bits also deals implicitly with the probability of receiving an error bit.... but we'll get to that in a bit (no pun intended)
Lets say for example, you have a 4-bit data package that gets sent wirelessly through a noisy environment. On the receiving end, there's no way the receiver would know if the package it received is representative of what the actual data. WIthout that parity bit, that receiver must assume that it represents the actual data. Now, this is where probability comes into play. What is the probability that the receiver will receive a '1' instead of a '0'? Since the majority of bits are defined as 0V for '0', and 5V for '1', you can see that it would take A LOT of noise to corrupt the data. For the sake of simplicity, lets just say the probability of receiving a corrupt bit is 1 in 1 million, which is a conservative guess. So what's the probability of receiving two corrupted bits in the same data package? It would be something like 6*10^6*10^6, or 1 in 6 trillion. Without that parity bit, your error rate would be 1 bit for every 1 million bits sent. With 1 parity bit, your error rate would be 1 bit for every 6 trillion bits sent since it will catch the single bit error, but wouldn't catch the error if 2 bits were corrupted. With 2 parity bits, your error rate next to nothing since each parity bit can check two of the four data bits for corruption. Even if the parity bits got corrupted, it would indicate a corrupt data package, and the receiver would tell the host to re-sent the package.
However, the downside to using 2 parity bits as suppose to one is that you just increased the required bandwidth by 50%.
There are MANY elaborate ways to validate data, and odd/even parity checking is the most simplest.
It is nothing more than a checksum bit (or bits) that lets the receiver know if the data package received has been corrupted. The concept of parity bits also deals implicitly with the probability of receiving an error bit.... but we'll get to that in a bit (no pun intended)
Lets say for example, you have a 4-bit data package that gets sent wirelessly through a noisy environment. On the receiving end, there's no way the receiver would know if the package it received is representative of what the actual data. WIthout that parity bit, that receiver must assume that it represents the actual data. Now, this is where probability comes into play. What is the probability that the receiver will receive a '1' instead of a '0'? Since the majority of bits are defined as 0V for '0', and 5V for '1', you can see that it would take A LOT of noise to corrupt the data. For the sake of simplicity, lets just say the probability of receiving a corrupt bit is 1 in 1 million, which is a conservative guess. So what's the probability of receiving two corrupted bits in the same data package? It would be something like 6*10^6*10^6, or 1 in 6 trillion. Without that parity bit, your error rate would be 1 bit for every 1 million bits sent. With 1 parity bit, your error rate would be 1 bit for every 6 trillion bits sent since it will catch the single bit error, but wouldn't catch the error if 2 bits were corrupted. With 2 parity bits, your error rate next to nothing since each parity bit can check two of the four data bits for corruption. Even if the parity bits got corrupted, it would indicate a corrupt data package, and the receiver would tell the host to re-sent the package.
However, the downside to using 2 parity bits as suppose to one is that you just increased the required bandwidth by 50%.
There are MANY elaborate ways to validate data, and odd/even parity checking is the most simplest.
Sorry, adding a parity rate does NOT decrease the error rate. It just lets you know the error.
To the original poster, if you want to learn what all this is really about, google for "redundant code". If you go beyond Parity toward ECC, make sure you bring something for your headache.
Quote:
Parity checking is a primitive character-based error detection method. The characters are encoded so that an additional bit is added to each character. The additional bit is to 0 or 1 according to the number of bits set in the character. The resulting number is either even or odd. There extra bit is set according to this result and according to which parity setting, either even or odd, is being used. If even parity is used, the extra bit is always set so that the codeword always contains an even number of bits set. In even parity, the number of bits set in the codeword is always odd. The decoding is done simply by checking the codeword and removing the extra bit. The parity checking will only detect one bit error bursts in each codeword. Parity checking has been used in character-based terminals but it is not useful for today's reliable communications. However, it is being used in memory chips to ensure correct operation.
regards, Peter
To the original poster, if you want to learn what all this is really about, google for "redundant code". If you go beyond Parity toward ECC, make sure you bring something for your headache.
Quote:
Parity checking is a primitive character-based error detection method. The characters are encoded so that an additional bit is added to each character. The additional bit is to 0 or 1 according to the number of bits set in the character. The resulting number is either even or odd. There extra bit is set according to this result and according to which parity setting, either even or odd, is being used. If even parity is used, the extra bit is always set so that the codeword always contains an even number of bits set. In even parity, the number of bits set in the codeword is always odd. The decoding is done simply by checking the codeword and removing the extra bit. The parity checking will only detect one bit error bursts in each codeword. Parity checking has been used in character-based terminals but it is not useful for today's reliable communications. However, it is being used in memory chips to ensure correct operation.
regards, Peter
What do you mean it doesn't decreases your error rate? In a 1-bit parity checking system, if there are two error bits in the data package, the parity bit will still show a correct parity on the data. So you still receive the corrupted package. That is, assuming that the receiver can re-request the data packet to be resent.
You answered that yourself, all you get is error detection. Re-requesting the data is OK for disturbed transmissions, but in the case of RAM that I assume we're talking about here, you have disturbed source data, and gone is gone then.
"Error rate" btw refers to the amount of wrong data that get to the actual receiver. What's been corrected on the way does not count.
That's why 8+1 parity mode has been replaced with the much more redundant 64+8 ECC coding. The neat trick is it's not using more storage. Just couple eight bytes together, and use their eight parity bits together too. This allows correction of all single-bit errors, many 2-bit errors, and detection of all 2-bit errors and some higher. Chipset maker ServerWorks got carried away on the concept, doing a 512+64 ECC across an entire SDRAM burst of eight transmissions. They claim full correction of up to 4-bit errors and detection of up to 8-bit errors.
The idea of redundancy is to put a distance between valid code words, by using a larger code space. Hamming Distance is your friend.
Without parity, all code space is filled with valid code words. Bit errors can neither be detected nor corrected, since no matter what you read, it looks valid. In byte storage, you have 2^8 valid words in a code space of 2^8.
8+1 parity widens the code space to 2^9 = 512 different values. Because you have 256 valid words, you can detect single bit errors, but not do a correction (because from an invalid word, you can't determine a unique "nearest" valid word).
64+8 ECC gets you 2^64 valid words in a huge 2^72 element code space. Lots of room to sprinkle the valid data words into, so that a good error detection and correction can be done.
512+64 is really insane.
http://www.cs.ucl.ac.uk/staff/S.Bhatti/D51-notes/node30.html
regards, Peter
"Error rate" btw refers to the amount of wrong data that get to the actual receiver. What's been corrected on the way does not count.
That's why 8+1 parity mode has been replaced with the much more redundant 64+8 ECC coding. The neat trick is it's not using more storage. Just couple eight bytes together, and use their eight parity bits together too. This allows correction of all single-bit errors, many 2-bit errors, and detection of all 2-bit errors and some higher. Chipset maker ServerWorks got carried away on the concept, doing a 512+64 ECC across an entire SDRAM burst of eight transmissions. They claim full correction of up to 4-bit errors and detection of up to 8-bit errors.
The idea of redundancy is to put a distance between valid code words, by using a larger code space. Hamming Distance is your friend.
Without parity, all code space is filled with valid code words. Bit errors can neither be detected nor corrected, since no matter what you read, it looks valid. In byte storage, you have 2^8 valid words in a code space of 2^8.
8+1 parity widens the code space to 2^9 = 512 different values. Because you have 256 valid words, you can detect single bit errors, but not do a correction (because from an invalid word, you can't determine a unique "nearest" valid word).
64+8 ECC gets you 2^64 valid words in a huge 2^72 element code space. Lots of room to sprinkle the valid data words into, so that a good error detection and correction can be done.
512+64 is really insane.
http://www.cs.ucl.ac.uk/staff/S.Bhatti/D51-notes/node30.html
regards, Peter
In fact, the example in the link actually shows how not to do it.
Valid datawords:
10000
01100
10011
If the receiver gets 10001, it knows that it's wrong (error detected), but can't correct since the distance to 10000 is the same as to 10011. There's your uncorrectable error. System Halted.
The above code has a Hamming Distance of 2 between its valid words. That gives you detection of all single bit errors and some higher order errors, but no correction.
These are better:
http://www.cs.ucl.ac.uk/staff/S.Bhatti/D51-notes/node32.html#SECTION00045000000000000000
http://www.cs.ucl.ac.uk/staff/S.Bhatti/D51-notes/node33.html#SECTION00046000000000000000
Valid datawords:
10000
01100
10011
If the receiver gets 10001, it knows that it's wrong (error detected), but can't correct since the distance to 10000 is the same as to 10011. There's your uncorrectable error. System Halted.
The above code has a Hamming Distance of 2 between its valid words. That gives you detection of all single bit errors and some higher order errors, but no correction.
These are better:
http://www.cs.ucl.ac.uk/staff/S.Bhatti/D51-notes/node32.html#SECTION00045000000000000000
http://www.cs.ucl.ac.uk/staff/S.Bhatti/D51-notes/node33.html#SECTION00046000000000000000
Hi there,
I have a question, and it's not regarding the topic, instead it's regarding the topic headline:
"Give me an uber geek super description of how parity works."
OK, here we go:
I read the word "uber" now several times, and I'm wondering is this new "in-language" and is it often used at you in the USA?
uber-geek, uber-soldier (Return to Castle wolfenstein ) , ......
I am wondering because maybe it's from the German word "über-" which means something like "over-"
Just speculation...
Thanks for your reply, even if it's not on topic!
Greetings
Bene
I have a question, and it's not regarding the topic, instead it's regarding the topic headline:
"Give me an uber geek super description of how parity works."
OK, here we go:
I read the word "uber" now several times, and I'm wondering is this new "in-language" and is it often used at you in the USA?
uber-geek, uber-soldier (Return to Castle wolfenstein
) , ......I am wondering because maybe it's from the German word "über-" which means something like "over-"
Just speculation... Thanks for your reply, even if it's not on topic!
Greetings
Bene
Benedikt, maybe because it sounds cool?
I have no idea at all what you guys are talking about, but I am trying. Just want to know where you all are picking this stuff up? I am working towards my EE and I have never seen stuff like this! Anyway, the math displayed here is pretty good stuff. And here I thought ECC was a marketing term! lol...
I have no idea at all what you guys are talking about, but I am trying. Just want to know where you all are picking this stuff up? I am working towards my EE and I have never seen stuff like this! Anyway, the math displayed here is pretty good stuff. And here I thought ECC was a marketing term! lol...
If you're in EE school, borrow some lecture material from CS classes. At least in techy CS, you get to learn how the math behind that stuff works. Vectors. Matrices. Headaches. So did I
w00t! Unfortunatly, I am taking corrispondance courses right now. When I get back to school, I will be sure to find a good prof who knows something... (I went to a community college before)
Lets see if I can remember how this works.
For serial communication, with 8bit data and a parity bit, (this chages depending on the protocal used, but it'll give you the basic idea)
at the start of communication, a high bit represents an idle state, when the signal goes low this means "the data is next", the next 8 bits are data and the 9th is the parity bit. After this the signal must go high, if it doesn't this means there was a frame error (more than 9 bits were recieved) and the data must be resent.
Example:
11111111001010010111111111111
the bold part is the data + parity
the data is 01010010 and a parity is 1
In EE, you don't necessarily ever learn this stuff. You can however usually take some Computer Engineering electives that will cover this. I'm currently taking "Microprocessor Orginization" where you go over all the basics of stuff like this. Next semester I take "Fundamentals of Computer Architecture" which is more indepth. If you find this stuff interesting, I highly recommend you try to take similar classes as electives.
Might i direct this discussion more towards parity with reference to RAM ? The argument - whether or not you can have EDO RAM that features parity. I say yes since on all parity ram i've seen (including that within this computer) the chip that handles the parity checking is different from the rest. Thus i must conclude that one can have chips just the same as any other that actually store the data, and you just add a chip that adds the parity bit to the data coming from the RAM iteself, thus its quite possible to have EDO parity ram. Anyone like to back me up or shoot me down please ? THanks
What you saw there is a symptom of the transitional times (parity to ECC) back then.
For both Parity and ECC, you need 72-bit wide storage. That's what you got on a pair of 36-bit wide parity/ECC SIMMs, typically made from 9 pieces of 4-bit-wide RAM.
Now for ECC with its 64+8 math, the entire width is read and written all the time. No partial access. However for old-style 8+1 Parity, byte-wise read/write operations are performed. Consequently, the 9th chip on each DIMM, while still being 4-bit-wide, must allow partial (single-bit-width) access. That's why you saw different chips there - they are special 4-bit-wide devices that have bit-lane-enable signals.
Now that noone does Parity anymore, those special chips have vanished, and ECC DIMMs simply have extra chips on to provide the extra 8 bits of width.
And then of course there were those not-really-Parity SIMMs, that didn't have an extra four bits of RAM width, but instead had a parity generator logic chip on that calculated the extra bits on the fly from the data lines of the other chips. Timing-wise, these were terrible because of the calculation delay, and of course, this totally defeats the purpose since you'll never see a parity error from them.
For both Parity and ECC, you need 72-bit wide storage. That's what you got on a pair of 36-bit wide parity/ECC SIMMs, typically made from 9 pieces of 4-bit-wide RAM.
Now for ECC with its 64+8 math, the entire width is read and written all the time. No partial access. However for old-style 8+1 Parity, byte-wise read/write operations are performed. Consequently, the 9th chip on each DIMM, while still being 4-bit-wide, must allow partial (single-bit-width) access. That's why you saw different chips there - they are special 4-bit-wide devices that have bit-lane-enable signals.
Now that noone does Parity anymore, those special chips have vanished, and ECC DIMMs simply have extra chips on to provide the extra 8 bits of width.
And then of course there were those not-really-Parity SIMMs, that didn't have an extra four bits of RAM width, but instead had a parity generator logic chip on that calculated the extra bits on the fly from the data lines of the other chips. Timing-wise, these were terrible because of the calculation delay, and of course, this totally defeats the purpose since you'll never see a parity error from them.
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