FX62 to have L3 cache

[Hard Ball]

http://www.theinquirer.net/?article=29738

This article from the Inq reports that FX62 and successors will have L3 built in at 4MB, to counter the large caches of the Conroe XE.

Can anyone confirm?

 

[Furen]

I dont think the FX-62 will have the L2 cache but rather the "next generation AM2" ones will. I'd say we'll see this L3 in Opterons before we see it on the FX series but perhaps the FX-64 will fit the timeline nicely.

 

[Duvie]

In the AM2 article I just read yesterday they said they were staying with the same naming scheme and mentioned FX62 as an AM2 socket....

The added L3 cache if an improved density sram like the AM2' rumore new L2 cache will help like the original EE chip for the prescott did....However as always not all programs will take advantage of the cache. I bet games, superpi, some other calculation app programs that work in under 4mb files will do nicely.....Multimedia video/ and audio as well as 3d CAD generation likely still will not...

 

[Skott]

Yeah, they said the FX-60 was the last of the 939 chips so if true the FX-62 should be a AM2 socket. Which is some type of 940 I think. Has more pins anyway.

 

[robertk2012]

L3 helps with many things in general. It made a big difference for the g4's back in the day. I guess the architecture will matter too. So who knows.

 

[Brunnis]

The FX-62 is probably not going to have it. It's not too far fetched to think that AMD will get an FX-64 with 4MB L3 out to counter Conroe XE when it's released later this fall. I'm wondering about the chip area, though. It's going to be pretty big! With some luck it will be the first 65nm CPU from AMD and that would definately help bring down the area.

 

[Cooler]

in five year we will see cpus that have 512mb of L2/L3. So most program could be stored in the cpu then if the dont get much bigger then todays and then ram accesse would be mute issue other then loading.

 

[aka1nas]

The better question is will this 4MB of L3 cache be shared between two cores or is it 2MB per core?

 

[Furen]

I think shared, which is better, considering that there wont be duplicate data. I doubt we'll see more than 8-16MB L2 per core within the next 5 years. Remember that 5 years ago 256k was all the rage and having more than 2MB per core still hasn't happened. This is specially true with AMD cpus which only have around 4 times the cache they did back then (1MB per core).

 

[formulav8]

I for one do NOT see this making a big difference in the performance for the most part. Unless the Cache is VERY fast and not just at cpu speed.

The memory controller really negates the need for large caches. But if its super fast cache, then yeah, it could make a nice difference in certain situations, gaming being one of them.

Just like I Don't see the PM/Solo/Duo cpu's gaining that much with a onboard memory controller since it already has a Huge L2 cache which negates accesses to the memory sub-sytem. Some apps will like it, but for the most part, it will NOT be any increases like the Athlon got from it. Especially when the Duo/Solo moves to 4MB Caches.

I of course could be Wrong on ALL counts 🙂


Jason

 

[coldpower27]

Originally posted by: Cooler
in five year we will see cpus that have 512mb of L2/L3. So most program could be stored in the cpu then if the dont get much bigger then todays and then ram accesse would be mute issue other then loading.

Doubtful at best, 512MB is practically insane even for 5 years.

For the 65nm generation it seems, 16MB LV3 is about what we can put on, with decent yield, on x86 CPU's anyway, Intel is doing this with their Xeon MP NetBurst Dual Core Tulsa.

So by 2011, which is 5 years from now, we should be into the late 32nm generation, with 22nm just around the corner.

Extrapolating from what I think is a reasonable estimate, 16MB LV3 per Socket on 65nm, 32MB LV3 per Socket on 45nm, and 64MB of LV3 per Socket on the 32nm generation, your looking at 128MB of LV3 per Socket on 22nm, however don't expect these CPU's to be consumer level, probably like Xeon MP, or the Opteron 8xx Series level.

If on 90nm were looking maybe 170mm2 for 4MB of LV3 cache which is doable, as if you add to the 220mm2 or so of the Opteron DDR2 Dual Core, your looking at almost 400mm2 which is in the neighborhood of Intel's Potomac-8MB on 90nm node.

 

[letdown427]

But the point of cache is that it is quickly addressable and useable, so a huge cache would mean latency... not to mention a huuuuge chip size. meh, that's the impression i got anyway.

 

[TrevorRC]

Originally posted by: Cooler
in five year we will see cpus that have 512mb of L2/L3. So most program could be stored in the cpu then if the dont get much bigger then todays and then ram accesse would be mute issue other then loading.

I don't believe that.

You don't even know if semi-conductors will still be used in five years. Let alone whether or not we'll still be using cache.

Also, do you realize how chip fabrication works? 512MB (so far as I know) would be physically impossible for a 45nm chip.
(Which is what we'll PROBABLY be using in 5 years)

 

[Pr0phetX]

hey i just bought an fx60 if i rma it to amd do you think they'll let me upgrade to an am2 chip? Even if i pay extra?

 

[Cooler]

Originally posted by: Pr0phetX
hey i just bought an fx60 if i rma it to amd do you think they'll let me upgrade to an am2 chip? Even if i pay extra?

I dont think they have step up program.

 

[imported_michaelpatrick33]

I wonder if the L3 cache is more for the quadcores and the upcoming pci-ex bus integration of the 1207 pin socket Opterons. Interesting stuff. Maybe AMD is playing its cards close to the vest and maybe they're ready for another typical AMD shoot themselves in the foot. I love specuation.