seeing so many messages on the internet talking about problems associated with VIA's PCI Bus Controller, I determined to make a few experiment.
I used Athlon XP 1600+, 128MB PC2100 DDR SDRAM, Epox 8KHA+, Quantum Fireball CR 8.4G, Seagate Barracuda IV 20G, Promise Ultra66 Controller.
I downloaded the VIA's own PCI Latency patch for Promise Ultra ATA controller. wpcredit was used to see what kind of modification did that patch do to M/B. HDTach 2.61 was used to measure the burst rate of the Ultra66 Controller.
The result appeared was quite confusing. Before the patch is applied, the burst read rate was 56.7MB/s. After the patch is applied, the burst read rate was 59.8MB/s. Further analysis showed that VIA's own patch only modified two registers inside KT266A chipset, while it changed quite a few registers in Promise Ultra66 controller. The information from www.tecchannel.de showed this patch increased the burst length from 24 packages to 120 packages.
I remembered a few months before this I asked FIC a question about a problem regarding "Windows Registry corrupted" when Norton Utilities 2001 WinDoctor did registry integrity scan on my VA-503+ M/B. Their response is: "because of the implementation of VIA's PCI bus, the arrangement of PCI INT lines in VIA's PCI bus are opposite to the PCI bus found on Intel chipset." This caused the problem I encountered. From this piece of information I guessed that VIA's PCI bus implementation is different from anyone else in this field. I think this is the cause of many problems we have with VIA's PCI bus.
To resolve this problem, I think the PCI devices have to optimize for VIA's PCI bus (just like what VIA's PCI patch does with Promise Ultra ATA controller), or VIA just simply has to follow Intel's PCI bus implementation.
This is just preliminary information, and more test will be carried out this week, with more hardware testing. I will let you know what happened, if I find any information.
Barracuda IV only has a maximum burst read rate of 50.4MB/s, when used with Promise Ultra66 Controller. It did not improve at all with either patch from George or VIA.
For George's PCI Latency patch, the only setting that increases the burst length of the PCI bus is the one that sets the PCI bus controller's latency to 0. Default value is 8 for KT266A. This increases the burst length of VIA PCI bus from 24 to 32 data cycles, and thus helps all the devices hooked onto the PCI bus. Excellent work, George.
I used Athlon XP 1600+, 128MB PC2100 DDR SDRAM, Epox 8KHA+, Quantum Fireball CR 8.4G, Seagate Barracuda IV 20G, Promise Ultra66 Controller.
I downloaded the VIA's own PCI Latency patch for Promise Ultra ATA controller. wpcredit was used to see what kind of modification did that patch do to M/B. HDTach 2.61 was used to measure the burst rate of the Ultra66 Controller.
The result appeared was quite confusing. Before the patch is applied, the burst read rate was 56.7MB/s. After the patch is applied, the burst read rate was 59.8MB/s. Further analysis showed that VIA's own patch only modified two registers inside KT266A chipset, while it changed quite a few registers in Promise Ultra66 controller. The information from www.tecchannel.de showed this patch increased the burst length from 24 packages to 120 packages.
I remembered a few months before this I asked FIC a question about a problem regarding "Windows Registry corrupted" when Norton Utilities 2001 WinDoctor did registry integrity scan on my VA-503+ M/B. Their response is: "because of the implementation of VIA's PCI bus, the arrangement of PCI INT lines in VIA's PCI bus are opposite to the PCI bus found on Intel chipset." This caused the problem I encountered. From this piece of information I guessed that VIA's PCI bus implementation is different from anyone else in this field. I think this is the cause of many problems we have with VIA's PCI bus.
To resolve this problem, I think the PCI devices have to optimize for VIA's PCI bus (just like what VIA's PCI patch does with Promise Ultra ATA controller), or VIA just simply has to follow Intel's PCI bus implementation.
This is just preliminary information, and more test will be carried out this week, with more hardware testing. I will let you know what happened, if I find any information.
Barracuda IV only has a maximum burst read rate of 50.4MB/s, when used with Promise Ultra66 Controller. It did not improve at all with either patch from George or VIA.
For George's PCI Latency patch, the only setting that increases the burst length of the PCI bus is the one that sets the PCI bus controller's latency to 0. Default value is 8 for KT266A. This increases the burst length of VIA PCI bus from 24 to 32 data cycles, and thus helps all the devices hooked onto the PCI bus. Excellent work, George.
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