Chipmakers keep secrets at IEDM
Posted: 14 Dec 2010 Print Version Bookmark and Share Subscribe
Linear Technology Corporation
Keywords: International Electron Device Meeting transistor process
The number of relevant papers presented at the 2010 International Electron Device Meeting (IEDM) declined compared to previous years. There was also a lack of consensus about the transistor structure for the future nodes, and despite emerging technologies, chipmakers say that economics and cost will drive their future transistor and process decisions.
The chase after Moore’s Law drove chipmakers in the past to keep developing leading-edge processes as quickly as they could, which led to a plethora of relevant papers at IEDM. Today, however, there are fewer leading-edge chipmakers, contributing to a ''big drop" in papers at this year’s event, said Meikei Ieong of Taiwan Semiconductor Manufacturing Co. Ltd (TSMC) and general chairman at IEDM. ''I don’t see (the amount of IEDM papers from the peak years) coming back," he said during an event.
There are other reasons for a decline in papers. In the past IEDM events, leading-edge chipmakers were more open and would often provide a hint on what’s coming on the horizon. IBM, Intel, Samsung, Toshiba, TSMC, UMC and others would reveal their latest and greatest processes amid an avalanche of papers.
At this years’ event though, few papers that provided clues on vendors' plans. Chipmakers kept their cards close to the vest and didn’t want to reveal their directions to their rivals. Many papers were academic in nature or were short on detail.
In place of clear presentations on plans for 22-/20nm plans, rumors abounded, with many believing the leading-edge foundries will extend bulk CMOS.
One big source of speculation is what Intel Corp. will do at that node. Some say Intel will extend bulk CMOS. Others think the chip giant could go to fully-depleted-or sometimes called extra thin silicon-on-insulator (SOI). One source even thinks Intel is looking at tri-gate structures at 22- or at 15-nm.
The wild card among the technology candidates is 3D based on through-silicon vias (TSVs), which is not process dependent. If chipmakers can produce TSV-based 3D chips in volumes-and at reasonable costs-it could throw a wrench in the entire roadmap.
Right now, leading-edge chipmakers are using conventional bulk CMOS and planar transistor structures for the 32-/28nm nodes. But clearly, there is still ''angst over the 20nm node and what transistor would be picked," said G. Dan Hutcheson, CEO, VLSI Research Inc. ''As for transistor structure, the safe bet is that we will extend conventional CMOS another generation."
Joanne Itow, an analyst with Semico Research Corp., agreed-and for good reason: Cost. It is simply too expensive and risky to move new and exotic transistor structure at 22-/20-nm, Itow said.
Just how long chipmakers will be able to extend today’s bulk CMOS remains murky. After 22-/20-nm, there is little agreement among chipmakers about the de facto transistor structure for the 16nm logic node, which is expected to appear in 2013 or so. There are a number of candidates on the table: III-V, bulk CMOS, FinFET, fully-depleted SOI, multi-gate, among others.
And 16nm, the field is wide open between current technologies as well as a range of exotic structures, such as III-V, carbon nanotubes, graphene, quantum well FETs, among others.
Analog, digital, memory measures
The semiconductor world remains divided between three camps: analog/mixed-signal, digital and memory.
Analog still uses trailing-edge processes and older fabs. But some believe that today’s analog fabs will hit the wall at 0.25-micron or so, causing vendors to either build new plants, or, in a more likely scenario, they will outsource more production to the foundries.
The memory community is facing a different problem. DRAM makers, which are at the 3xnm node, claim they will be able to scale at least to the 1x node. NAND flash vendors, which are at the 2xnm node, are singing the same tune.
If or when today’s memory runs out of steam, the memory houses are also exploring next-generation technologies like FeRAM, MRAM, phase-change and ReRAM. Meanwhile, the shift to 1xnm DRAM and NAND largely depends on the readiness of a next-generation lithography technology called extreme ultraviolet (EUV), which has been beset by delays and technical problems. Current 193nm immersion is reaching its limits in terms of resolution.
ASML Holding NV is working hard to ready its first production-like EUV tool, which is expected to ship in the near future. It’s unclear if the tool will work in production fabs-at least for now.
The logic community also wants EUV sooner than later. ''We would love to have EUV now," said Mark Bohr, Intel Senior Fellow and director of process architecture and integration at Intel.
Intel
In interviews, Intel technologists have said they are not counting on EUV for the 22nm node. In fact, Intel may extend 193nm immersion to the 11nm node, thereby pushing out the need for EUV.
Last year, Intel rolled out a working SRAM cell using 22nm technology. Beyond that, the chip giant has not officially announced its 22nm process, nor has it given details about it.
''We believe Intel will introduce a germanium (III V) channel and full depleted SOI at 22-nm. This will give Intel a quantum leap in performance over what they are achieving and leave competitors 3-5 years behind. The 22nm process should be in manufacturing at Intel in Q4 2011," said Gus Richard, an analyst with Piper Jaffray & Co., in a recent report. SOI uses a layered silicon-insulator-silicon substrate in a device, which is supposed to reduce parasitic capacitance and improve performance.
Others disagree. “I don’t think Intel is going with SOI at 22nm," Itow said.
''There are clues about Intel, but in reality, they (nor anyone else, for that matter) have locked down any decisions," VLSI’s Hutcheson said. ''They have to first finish figuring out what options work and what the transistor characteristics will be. Then focus on which ones in what combinations make the lowest cost wafers with the highest yields. Intel’s generally more conservative, which gets them first to market. So I would bet they will figure out how to do it with conventional CMOS."
Bohr said that Intel has ''no intention of using the thick version of SOI," but he acknowledged that the company is ''exploring" fully-depleted SOI. Hedging its bets, Intel is also quietly working on TSV-based 3D technology. Bohr said there are still many technical challenges with the technology. ''It’s still two or three years away," he said.
3D TSV
Experts define a true 3D package as one that stacks various chips vertically and then connects them by deploying TSVs. The aim is to shorten the interconnections between the chips, reduce die sizes and boost device bandwidths.
So far, chipmakers are shipping limited 3D devices based on TSVs, mainly CMOS image sensors, MEMS, and, to some degree, power amplifiers. There are several problems with TSV technology: Lack of EDA design tools; complexity of designs; integration of assembly and test; cost; and lack of standards.
Initially, chipmakers could move towards a so-called 2.5D device based on an interposer technology, which could hit the mainstream in 2012 or so. A full-blown TSV-based 3D chip may not hit the mainstream until 2013 to 2015, according to analysts.
Still, despite the challenges, IBM Corp. claims to have already demonstrated the viability of TSV-based 3D devices. ''There are no showstoppers" for TSV-based 3D, said Subramanian Iyer, fellow, systems and technology group, IBM.
IBM and its partners, of course, are also exploring a range of transistor structures for the 22-/20nm node and beyond. One partner, GlobalFoundries Inc., has rolled out its 20nm process.
Beyond that, there is no clear-cut winner in the next-generation transistor race. ''I don’t think it’s very clear," Iyer said, ‘’but I think you have to go to fully-depleted" SOI in future nodes.
One vendor put the debate in perspective. Cost remains the key in transistor development and chip manufacturing, said Jim Clifford, senior VP and general manager of operations for Qualcomm Inc..
In the process technology curve from 90nm until now, the transistor cost curve has dropped by 29 percent per node. ''If the curve flattens, Jim is worried," Clifford said, referring to himself. The industry ''needs to focus on extending semiconductor economics."
- Mark LaPedus
EE Times
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