Fudzilla: New AMD Zen APU boasts up to 16 cores (plus Greenland GPU with HBM)

Page 62 - Seeking answers? Join the AnandTech community: where nearly half-a-million members share solutions and discuss the latest tech.

Dresdenboy

Golden Member
Jul 28, 2003
1,730
554
136
citavia.blog.de
Just to put it into perspective, that's about the performance leap from Nehalem to Haswell. In one generation. You really think that's feasible?

With the Core 2, we knew that it was at least in the realm of possibility that it might outperform the Athlon 64 X2, since the Pentium M and then Core 1 were already putting up a far better fight than the Netburst CPUs were. I don't doubt that AMD could produce a decent processor by pulling the old K10.5 core from Llano out of mothballs and splicing in the execution unit improvements and instruction sets from the Bulldozer+ line, but something competitive with Skylake (possibly even Cannonlake) in terms of IPC? That seems a pretty massive ask.
It would be a pretty massive task. AMD would loose all their efforts regarding design automation, HDL, etc. Also changes of the process characteristics would require new design paradigms to adapt to new market requirements. They surely will reuse existing ideas and logic (on a RTL level at least) if appropriate.

The Nehalem -> Haswell path is an evolutionary one. This is not comparable to Excavator -> Zen. It's likely more a change like Prescott -> Intel Core (or later Nehalem).
 

Enigmoid

Platinum Member
Sep 27, 2012
2,907
31
91
Take Excavator, add 40% higher IPC. Eliminate the CMT penalty and add HyperTthreading, lower power consumption by 50-60% and add 8 cores 16 threads.

Now a 4 core 8 thread Skylake socket 1151 will not be able to compete against an 8 core 16 threads ZEN, only Skylake-E can at the same core/threads count.

And all that IPC will come at a 0:1 power: IPC budget. :rolleyes: If IPC increases 40% expect core power usage to increase at least 20% (1:2) but likely 40% (1:1). Or are you really expecting twice the performance at half the power usage?

IF ZEN is a beefed up core its going to consume proportionally more power.

Sure if it clocks decently, also the CMT penalty hit will be taken out & HT benefits be added. A single Zen core (plus HT) should be much better than one Excavator module & if everything goes according to plan that should bring them closer to Haswell IPC or even exceed it in fringe cases. Remember Intel can be beaten in terms of raw performance, POWER8 & the upcoming POWER9 outperform it in certain tasks & the same should be the case on desktops with Zen. It's not necessarily a case of "core for core" parity, on desktops, as AMD only needs to beat them in perf/$ to be relevant here again.

Power 8 guzzles down power like no tomorrow.

AMD already beats intel in server perf/$ (for the raw CPU cost).
 

R0H1T

Platinum Member
Jan 12, 2013
2,582
162
106
And all that IPC will come at a 0:1 power: IPC budget. :rolleyes: If IPC increases 40% expect core power usage to increase at least 20% (1:2) but likely 40% (1:1). Or are you really expecting twice the performance at half the power usage?

IF ZEN is a beefed up core its going to consume proportionally more power.



Power 8 guzzles down power like no tomorrow.

AMD already beats intel in server perf/$ (for the raw CPU cost).
And you know this how, also the last server chip from AMD was on 32nm so this is what ~2.5 nodes better.

It still does good in terms of perf/W for the power it consumes unless you have evidence to the contrary.

Don't think that's the case with E3, the E5 & E7 possibly but not the former.
 

dark zero

Platinum Member
Jun 2, 2015
2,655
138
106
Just to put it into perspective, that's about the performance leap from Nehalem to Haswell. In one generation. You really think that's feasible?

With the Core 2, we knew that it was at least in the realm of possibility that it might outperform the Athlon 64 X2, since the Pentium M and then Core 1 were already putting up a far better fight than the Netburst CPUs were. I don't doubt that AMD could produce a decent processor by pulling the old K10.5 core from Llano out of mothballs and splicing in the execution unit improvements and instruction sets from the Bulldozer+ line, but something competitive with Skylake (possibly even Cannonlake) in terms of IPC? That seems a pretty massive ask.
If Intel did it, why AMD can't do it?
Similar thing with nVIDIA and AMD...
 

TheELF

Diamond Member
Dec 22, 2012
3,967
720
126
Yeah so,if the rumors are true,amd will raise IPC by 40% by going from 4 to 6 pipes, that's ~35% right there,so no (or very little) single thread gains at all.
Getting rid of CMT is a good call.
Adding SMT is also good,although looking at that picture the real core and the smt one are still going to compete for the same fpu,
and remember how awesome HT was on the pentium 4 ?
Yeah I don't hold big hopes for a first attempt at anything technological.

So a module has a total of 4+4=8 pipes and a new core will have 6 making the new zen quads still slower than the FX-8.

The only good thing that zen will have are gonna be high numbers in cinebench winrar and the likes,numbers that will probably come close to even skylake i7,amd is getting away with selling CPU's on those numbers alone for years now.

zen.jpg
 

Insert_Nickname

Diamond Member
May 6, 2012
4,971
1,691
136
Yeah so,if the rumors are true,amd will raise IPC by 40% by going from 4 to 6 pipes, that's ~35% right there,so no (or very little) single thread gains at all.
Getting rid of CMT is a good call.
Adding SMT is also good,although looking at that picture the real core and the smt one are still going to compete for the same fpu,
and remember how awesome HT was on the pentium 4 ?
Yeah I don't hold big hopes for a first attempt at anything technological.

So a module has a total of 4+4=8 pipes and a new core will have 6 making the new zen quads still slower than the FX-8.

The only good thing that zen will have are gonna be high numbers in cinebench winrar and the likes,numbers that will probably come close to even skylake i7,amd is getting away with selling CPU's on those numbers alone for years now.

zen.jpg

Actually, the interesting part on that slide is not the integer pipes, but the fact that AMD is moving to from 2 128bit FMACs to 2 256bit FMACs. The Bulldozer family has always had pretty decent integer performance, but FPU performance has been something of a sore spot.
 

Enigmoid

Platinum Member
Sep 27, 2012
2,907
31
91
And you know this how, also the last server chip from AMD was on 32nm so this is what ~2.5 nodes better.

It still does good in terms of perf/W for the power it consumes unless you have evidence to the contrary.

Don't think that's the case with E3, the E5 & E7 possibly but not the former.

He is comparing to excavator.

The point still stands. Increasing IPC generally comes at the cost of some increase of core power. At the same frequency and process neutral haswell consumes more power than westmere and westmere more power than conroe. Unless AMD is going to get that 40% IPC gain (and then HT gains) at the cost of absolutely no extra power the Zen core will consume more power than SR/EX at a given frequency (though do more work).
 

dark zero

Platinum Member
Jun 2, 2015
2,655
138
106
He is comparing to excavator.

The point still stands. Increasing IPC generally comes at the cost of some increase of core power. At the same frequency and process neutral haswell consumes more power than westmere and westmere more power than conroe. Unless AMD is going to get that 40% IPC gain (and then HT gains) at the cost of absolutely no extra power the Zen core will consume more power than SR/EX at a given frequency (though do more work).
Not at all... remember instructions... AMD getting most instructions from Intel Haswell that will boost their performance a LOT without increase the power consumption dramatically.
Definately it's the same scenario from Prescott to Conroe, even more dramatic considering the big node shrink (32 nm to 14nm).

On the APU side, things are less dramatic... since they are on 28nm right now.
 
Last edited:

NTMBK

Lifer
Nov 14, 2011
10,208
4,940
136
I'm most interested in what AMD does with their cache hierarchy. Hopefully Zen will have much improved latencies.
 

Tuna-Fish

Golden Member
Mar 4, 2011
1,324
1,462
136
Yeah so,if the rumors are true,amd will raise IPC by 40% by going from 4 to 6 pipes, that's ~35% right there,so no (or very little) single thread gains at all.

The slide that this rumour is based on has been confirmed to be a fake with absolutely no basis on reality.

Also, going from 4 to 6 pipes would not immediately raise IPC by 40%. With no other changes, the first added pipe would increase IPC by maybe 10% and the second by 5% tops. The hard part in modern CPUs is not executing the instructions, it's getting them where they need to be. The weakest part of BD is the caches.
 

Dresdenboy

Golden Member
Jul 28, 2003
1,730
554
136
citavia.blog.de
Actually, the interesting part on that slide is not the integer pipes, but the fact that AMD is moving to from 2 128bit FMACs to 2 256bit FMACs. The Bulldozer family has always had pretty decent integer performance, but FPU performance has been something of a sore spot.

These slides are very likely fakes as the accompanying ones, of which none were shown during any AMD event after the fake leak.
 

dark zero

Platinum Member
Jun 2, 2015
2,655
138
106
These slides are very likely fakes as the accompanying ones, of which none were shown during any AMD event after the fake leak.
If I am not wrong, despite the leaks were fake, the AMD staff said before that they will ditch the CMT and goes to SMT to improve the performance... so that means that they will return to Intel side..
 

Phynaz

Lifer
Mar 13, 2006
10,140
819
126
Take Excavator, add 40% higher IPC. Eliminate the CMT penalty and add HyperTthreading, lower power consumption by 50-60% and add 8 cores 16 threads.

You forgot to add the pixie dust and unicorn horn.




Really, that's you adding to the discussion?


esquared
Anandtech Forum Director
 
Last edited by a moderator:

Dresdenboy

Golden Member
Jul 28, 2003
1,730
554
136
citavia.blog.de
If I am not wrong, despite the leaks were fake, the AMD staff said before that they will ditch the CMT and goes to SMT to improve the performance... so that means that they will return to Intel side..
Maybe. There are many possible microarchitectures to add SMT to. And Jim Keller's previous designs had nothing in common with Intel's.
 
Last edited: