FSB and Hyper Transport

[hardwareking]

Call me a noob,if u want.
But can someone explain to me,the difference between hypertransport in amd systems and the FSB in intel systems?
Please......
And what does all the stuff about the FSB getting saturated mean?And doesn't AMD's hyper-transport get saturated?

 

[aka1nas]

In Intel and older AMD systems, the memory controller was located on the motherboard. For the purposes of your question, the FSB is the "pipe" that connects the northbridge (the chip that contains the memory controller among a few other things) to the CPU. Due to the integrated memory controller on the A64, there isn't really a traditional FSB anymore on such systems. The northbridge now only controls the AGP(now PCI-E) controller, or even ceases to exist as a seperate chip and has it's features bundled in with the southbridge(Handles IDE/SATA, USB, PCI, etc. Communicates via Hypertransport on K8 systems) to make a single chip solution.

In most systems, the FSB clock is/was the main clock most other subsystems were based off of. This is why, for example, a board without PCI/AGP locks OCs those buses out of spec when you OC the FSB.

HyperTransport is a next-gen interconnect scheme that currently operates at 1Ghz bi-directionally. In A64 systems, the memory controller is integrated on the CPU and the CPU is connected to the rest of the system via a HT link. This is faster than the FSB (most FSBs are running at 200Mhz these days), though most desktop systems don't need that much bandwith yet.

HT makes a bigger difference with Multi-core/Multi-CPU systems. Intel is currently hurting a bit there as Xeons currently have to both talk to the northbridge via a shared FSB. The high-end Intel SMP systems now have dual FSBs, but even this is a stopgap measure. Multi-socket Opteron systems use extra HT links between CPUs to do communication between chips. As their memory controller is already on the CPU, they don't all hog one "pipe" back to the northbridge and the RAM.

 

[TheRyuu]

It's pretty simple actually. Hypertransport is a serial interconnect (just like SATA) while FSB is an older paralell connect (like PATA). At least I think thats the way it is.

Hypertrasnport can send much more data than a FSB. I don't think I've ever seen a AMD HT link ever get saturated (meaning completly filled up and bottlenecked). I could probably turn my HT link down to 500mhz (that's 250x2 for me) and still wouldn't see and diff. compared to the stock 1ghz (2gh bi) that I have it running on now. YOu don't have to use a HT link just because you have a on-die memory controller. It just happen to work out that way, and work out really good.

However Intel's new Conroe architechture isn't as bandwidth limited as the Netburst one's are so the 1333mhz FSB isn't exactly a problem for desktops. However for severs, AMD's HT can do wonders, especally in 4 core and 8 core and even 16 core systems.

 

[zephyrprime]

As wizboy11 says, ht is a serial interconnect. Specifically, it is a modern differential signaling type of interconnect which is the key to its higher ultimate performance limitations versus a traditional fsb. (differential signaling is the advancement that has allowed for the creation of stuff like sata, usb, and etc.)

Also, the FSB is a "bus" because it allows for multiple things being connected to it at the same time. In the old days, both the chipset and the VESA Local Graphics slot sat on the front side BUS. Nowadays, the bussing abilities are still utilized by intel multicore chips which actually act like 2 separate chips riding on the same bus.
On the other hand, HT is a point-to-point interconnect meaning that only one device can connect on either end of the connection.

The issue to bus saturation on intel platforms exists because multi chip intel computers share a single memory controller which is located on the northbridge of the chipset. Basically, you have inadequate bandwidth for too many chips. AMD chips have integrated memory controllers so there are more connections to memory and hence more aggregate bandwidth. (In a way, the bus put out by the integrated memory controller on an AMD chip is a sort of FSB but nobody calls it that.)

 

[Viditor]

Some excellent answers...I'll try a very simple one.

A FSB is of course a "bus". This means that all of the data traffic to and from the CPU goes through it.
HT is a P2P (or point-to-point) connection. This means that rather than all of the data going through a single bus, there are several individual connections for the data.
The advantage is easily understood if you picture a single 8 lane highway which goes in both directions and has traffic cops to control the flow, versus 4 x 2 lane highways, each lane of which is one way in each direction.

There are 2 types of HT connections as well (they aren't all the same).
1. Normal HT - these go to things like the Southbridge of the chipset for things like the HDD or I/O, etc... These go through an HT controller
2. cHT (Coherent HT) - these are HT links that go directly to and from the cache of the CPU, and include connections to other CPUs.

 

[hardwareking]

thanks for the replies.And i think i truly understand now.
So is this the reason K8 was whooping netburst like there's no tomorrow?

 

[RichUK]

Originally posted by: hardwareking
thanks for the replies.And i think i truly understand now.
So is this the reason K8 was whooping netburst like there's no tomorrow?

No thats just partially the reason, the Hypertransport and the FSB models are just part of the processor subsystem, basically a means for processor communication.

The difference in architecture denoted the best performer (K8 Vs Netburst). If you notice Conroe (new arch), this still uses the same processor communication model (the FSB for all communication) and beats the K8 arch in pretty much all performance tests, this is down to a better design. Of course the addition of 65nm and more and unified level 2 cache aids in its better performance too, but this just simply proves that the FSB is not a hindrance yet for Intel?s subsystem.

Back then AMD's K8 was just simply a better design overall over Intel's Netburst design, they took different roots in designing the better performing chip.

AMD took the root of a high IPC with moderate frequency design, where as Intel had a lower IPC but a higher frequency design, the problem was a number of things that held net burst back, where the main issue was the heat that was generated. If not for this Netburst could quite well of scaled a lot further and surpassed AMD's K8. In the end Intel were only able to produce a retail 3.8Ghz model as its fastest brand based on the Prescott Netburst design.

 

[Viditor]

Originally posted by: RichUK

Originally posted by: hardwareking
thanks for the replies.And i think i truly understand now.
So is this the reason K8 was whooping netburst like there's no tomorrow?

No thats just partially the reason, the Hypertransport and the FSB models are just part of the processor subsystem, basically a means for processor communication.

The difference in architecture denoted the best performer (K8 Vs Netburst). If you notice Conroe (new arch), this still uses the same processor communication model (the FSB for all communication) and beats the K8 arch in pretty much all performance tests, this is down to a better design. Of course the addition of 65nm and more and unified level 2 cache aids in its better performance too, but this just simply proves that the FSB is not a hindrance yet for Intel?s subsystem.

Back then AMD's K8 was just simply a better design overall over Intel's Netburst design, they took different roots in designing the better performing chip.

AMD took the root of a high IPC with moderate frequency design, where as Intel had a lower IPC but a higher frequency design, the problem was a number of things that held net burst back, where the main issue was the heat that was generated. If not for this Netburst could quite well of scaled a lot further and surpassed AMD's K8. In the end Intel were only able to produce a retail 3.8Ghz model as its fastest brand based on the Prescott Netburst design.

Agreed...the long and short of it is that Intel have developed an excellent design for their new core. If and when AMD equal this, then once again AMD will have a distinct advantage because of their platform (which is why you hear all the speculation about K8L), but until then (once Conroe is available) Intel will own the performance crown.
The one place where AMD will keep their performance advantage (mainly because of the platform) is in Enterprise Servers (4+ processors). This is where the FSB starts to feel the pinch of the heavy data traffic...

The only AMD markets for the consumer going forward will be the mid to low end. Cheap X2 and Semprons should hold up fairly well (certainly against any of the Netburst chips...who would buy a PD 805 for $100 when he can get an X2 3800+ for $150?)

 

[hardwareking]

so basically the fsb bottleneck only occurs when dealing with multi-processor servers and quad-core processprs(i read that in some thread here).And does intel plan on having any reply to hyper-transport?

 

[aka1nas]

The FSB can be a bottleneck in dual-core CPUs (I.E. the pentium D) as well as dual socket systems. A lot of this has to do with the architecture of the CPU in question. Netburst chips depended heavily on memory bandwith to get good performance, and the Pentium D essentially put two Pentium 4s on one FSB and made them share the "pipe" to the memory controller.

Intel does have a newer interconnect scheme in development called CSI, but it has been delayed a few times so is not here yet.

 

[Viditor]

Originally posted by: aka1nas
The FSB can be a bottleneck in dual-core CPUs (I.E. the pentium D) as well as dual socket systems. A lot of this has to do with the architecture of the CPU in question. Netburst chips depended heavily on memory bandwith to get good performance, and the Pentium D essentially put two Pentium 4s on one FSB and made them share the "pipe" to the memory controller.

Intel does have a newer interconnect scheme in development called CSI, but it has been delayed a few times so is not here yet.

Agreed...
The most current roadmap from Intel shows CSI coming out between Q4 08 and Q2 09...

 

[pcoffman]

Originally posted by: hardwareking
does intel plan on having any reply to hyper-transport?

Intel's reply to MP servers (4-8 CPUs) will be Tigerton, sometime in 2007. Until then, I guess AMD will rule the x86 MP server space. I don't think that Tulsa (a Xeon MP to be released later this year) will seriously challenge AMD on the high x86 end.

Intel has a pretty good reply to AMD in Woodcrest, which is the Xeon 5100 series. This is a DP server, however, not MP.

Tigerton will be the first MP chip built on the new Core microarchitecture. It will also be quad-core and use that different interconnect technology that will replace the FSB.

In regard to FSB vs. HyperTransport, menory benchmarks are one of the few in which A64 can best Core 2. However, memory is just one subsystem, so overall the Core 2 chips perform better.

 

[Viditor]

Originally posted by: pcoffman

Originally posted by: hardwareking
does intel plan on having any reply to hyper-transport?

Intel's reply to MP servers (4-8 CPUs) will be Tigerton, sometime in 2007. Until then, I guess AMD will rule the x86 MP server space. I don't think that Tulsa (a Xeon MP to be released later this year) will seriously challenge AMD on the high x86 end.

Intel has a pretty good reply to AMD in Woodcrest, which is the Xeon 5100 series. This is a DP server, however, not MP.

Tigerton will be the first MP chip built on the new Core microarchitecture. It will also be quad-core and use that different interconnect technology that will replace the FSB.

In regard to FSB vs. HyperTransport, menory benchmarks are one of the few in which A64 can best Core 2. However, memory is just one subsystem, so overall the Core 2 chips perform better.

Mostly agree...
Tigerton is due around June 07, but the dual core K8L Opterons should be well and truly out by then as well. Personally, I don't think Tigerton will be able to keep up in the MP space.

What's interesting is that we (IMHO) will see a definite segmentation of products going forward...

Intel will own the low-end server space (after Woodcrest platforms are qualified and before K8L), and AMD will continue to own the high-end server space.

In consumer, Intel will own the mid-high end space, and AMD will own the low-mid end space...the real battle there will be on chip price and the "sweet spot". Again, the cards are shuffled once more when K8L is released...

For mobile, Intel will also own the high-end space, but AMD will own the low-mid end space. I don't see Meroms coming down in price too much because of their size (they're twice as big as Yonah).

 

[pcoffman]

Originally posted by: Viditor
Tigerton is due around June 07, but the dual core K8L Opterons should be well and truly out by then as well. Personally, I don't think Tigerton will be able to keep up

Interesting ...

 

[dmens]

Originally posted by: Viditor
In consumer, Intel will own the mid-high end space, and AMD will own the low-mid end space...the real battle there will be on chip price and the "sweet spot". Again, the cards are shuffled once more when K8L is released...

For mobile, Intel will also own the high-end space, but AMD will own the low-mid end space. I don't see Meroms coming down in price too much because of their size (they're twice as big as Yonah).

unlikely. turions are getting trashed on power-perf by yonah, and will get trashed even harder by merom. so until k8L is out, amd has no mobile answer. a low-end merom with only 2MB combined L2 (which is not much bigger than a yonah) can beat any k8.

as for desktops, take the power concerns out of the picture, and conroe is still kicking ass. value segment merom @ 1.8ghz will beat any amd part at the same price range.

once k8l comes out, we will see how it fits the mobile market, and that really depends on how the knobs were tweaked two years ago. but saying amd will "own" the low-mid end is also very premature, since nobody knows how 65nm amd parts will be priced. why would a new part on a new process be priced more competitively than a one year old part on a 18 month old process? it should be the other way around.

and since you brought up die size, have you seen how big K8L is? the reason the merom core expanded over yonah (minus the cache) was mainly the wider datapath, which is exactly what K8L incorporated, if rumors are to be believed.

 

[hardwareking]

so if i were to get a quad-core kentsfield,then i would suffer performance losses cause of bus saturation,right?
And how much does bus speed affect the bottleneck?And does intel's quad-pumped bus have anything to do with performance what so ever?

 

[pcoffman]

Originally posted by: hardwareking
so if i were to get a quad-core kentsfield,then i would suffer performance losses cause of bus saturation,right?

Kentsfield should experience no more performance loss due to the FSB than Core 2 processors currently suffer. The FSB of Core 2 may technically be a bottleneck, but it is not in practice affecting performance much. Kentsfield consists of two Core 2 Duos. Each Core 2 Duo will have its own FSB. So there should be no more of a bottleneck than current Core 2s.

And how much does bus speed affect the bottleneck?

It affects it some. For example, the Pentium D 805 has a 533MHz FSB (as opposed to the 800MHz FSB of, say, a 920). As you can see from these charts, it's a little slower. Part of this has to do with the 533MHz FSB.

And does intel's quad-pumped bus have anything to do with performance what so ever?

Not really. Intel's 800MHz FSB is just a 200MHz FSB quad-pumped (1066MHz is 266 quad-pumped). It's a noticeable bottleneck with NetBurst, not so much with Core 2.

 

[irwincur]

Kentsfield should experience no more performance loss due to the FSB than Core 2 processors currently suffer.

They will operate in different environments however.

The bus may be an issue in high demand, high capacity server applications - none of which have really been tested on Core 2. Actually the only semi-real server test I have seen on the Core 2 architecture has been an intensive Apache test where it was trounced by AMD's offerings.

So, the jury is out. I would bet that in a well used server, the FSB issue may become a problem.

 

[Accord99]

Originally posted by: irwincur
The bus may be an issue in high demand, high capacity server applications - none of which have really been tested on Core 2. Actually the only semi-real server test I have seen on the Core 2 architecture has been an intensive Apache test where it was trounced by AMD's offerings.

The GamePC using the built-in benchmark is not very intensive nor particularly realworld, unlike the one done by Johan using Apache, MySQL and PHP.

 

[pcoffman]

Originally posted by: irwincur
They [Kentsfield & Core 2] will operate in different environments

How so?

The bus may be an issue in high demand, high capacity server applications - none of which have really been tested on Core 2

Kentsfield and Core 2 are not server chips.

Actually the only semi-real server test I have seen on the Core 2 architecture has been an intensive Apache test

Woodcrest (Xeon 5100 series) has been tested here and here.

in a well used server, the FSB issue may become a problem

Maybe so. However, the first review above concludes "the performance lead we've seen from Woodcrest in nearly every test we have run bodes very well". The second that the Xeon 5160 "will simply be the most powerful server CPU this year".

Please note that the Xeon 5100 series is a DP, not a MP, higher end, server. For that, we have to wait for Tigerton.